Reset Settings - Freescale Semiconductor e200z3 Reference Manual

Register Model
Mnemonic
SPRG5 SPR general 5
SPRG6 SPR general 6
SPRG7 SPR general 7
SRR0 Save/restore register 0
SRR1 Save/restore register 1
SVR System version register
TBL Time base lower
TBU Time base upper
TCR Timer control register
TLB0CFG TLB0 configuration register
TLB1CFG TLB1 configuration register
TSR Timer status register
USPRG0 User SPR general 0
XER Integer exception register
Notes:
1
Only writable when multiple contexts are implemented. Otherwise, writes are ignored
2
The debug status register (DBSR) is read using mfspr. DBSR cannot be directly written. Instead, DBSR bits corresponding
to 1 bits in the GPR can be cleared using mtspr.
3
IVOR9 handles the auxiliary processor unavailable interrupt. This interrupt is defined by the EIS but not supported in the
e200z3; therefore, use of IVOR9 is not supported in the e200z3.
4
TSR is read using mfspr, but it cannot be directly written. Instead, TSR bits corresponding to 1 bits in the GPR can be cleared
using mtspr.
2.18.4

Reset Settings

Table 2-41 shows the state of the PowerPC Book E registers and other optional resources immediately
following a system reset.
Resource
Program counter
GPRs
2-74
Table 2-40. Special-Purpose Registers (continued)
Name
Table 2-41. Reset Settings for e200z3 Resources
p_rstbase[0:19] || 0xFFC
1
Unaffected
e200z3 Power Architecture Core Reference Manual, Rev. 2
SPR Number Access
261 Read only
277 R/W
262 Read only
278 R/W
263 Read only
279 R/W
26 R/W
27 R/W
1023 Read only
268 Read only
284 Write only
269 Read only
285 Write only
340 R/W
688 Read only
689 Read only
4
336 Read/Clear
256 R/W
1 R/W
System Reset Setting
Privileged e200z3-Specific
No No
Yes No
No No
Yes No
No No
Yes No
Yes No
Yes No
Yes Yes
No No
Yes No
No No
Yes No
Yes No
Yes Yes
Yes Yes
Yes No
No No
No No
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