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ESAI Data and Control Pins
THCKD
TFSD
0
0
0
0
1
1
1
1
SCKT may be programmed as a general-purpose I/O pin (PC3) when the ESAI SCKT function is not being
used.
Although the external ESAI serial clock can be independent of and
asynchronous to the DSP system clock, the DSP clock frequency must be at
least three times the external ESAI serial clock frequency and each ESAI
serial clock phase must exceed the minimum of 1.5 DSP clock periods.
8.2.9
Frame Sync for Receiver (FSR)
FSR is a bidirectional pin providing the receivers frame sync signal for the ESAI interface. The direction
of this pin is determined by the RFSD bit in RCR register. In the asynchronous mode (SYN=0), the FSR
pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode
(SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable
control (TEBE=1, RFSD=1). For further information on pin mode and definition, see
receiver clock signals see
When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR
register. When configured as the output flag OF1, this pin reflects the value of the OF1 bit in the SAICR
register, and the data in the OF1 bit shows up at the pin synchronized to the frame sync being used by the
transmitter and receiver sections. When configured as the input flag IF1, the data value at the pin is stored
in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network
mode.
FSR may be programmed as a general-purpose I/O pin (PC1) when the ESAI FSR function is not being
used.
8-6
Table 8-2 Transmitter Clock Sources
Transmitter
TCKD
Bit Clock
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Table
8-1.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Source
SCKT
HCKT
SCKT
HCKT
SCKT
HCKT
INT
HCKT
SCKT
HCKT
INT
HCKT
NOTE
OUTPUTS
SCKT
FST
FST
SCKT
SCKT
FST
FST
SCKT
Table 8-8
Freescale Semiconductor
and on
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