Pll Initialization - Freescale Semiconductor DSP56374 User Manual

DMA Request Source Bits
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001-11111
4.6

PLL Initialization

The following figure displays the PLL control register (PCTL). This register is used to control the PLL operation including its
multiplication/divide factors and enabling bits.
Freescale Semiconductor
Table 4-5. DMA Request Sources
DRS4...DRS0
External (IRQA pin)
External (IRQB pin)
External (IRQC pin)
External (IRQD pin)
Transfer Done from DMA channel 0
Transfer Done from DMA channel 1
Transfer Done from DMA channel 2
Transfer Done from DMA channel 3
Transfer Done from DMA channel 4
Transfer Done from DMA channel 5
Reserved
ESAI Receive Data (RDF=1)
ESAI Transmit Data (TDE=1)
SHI HTX Empty
SHI FIFO Not Empty
SHI FIFO Full
Reserved
Reserved
TIMER0 (TCF=1)
TIMER1 (TCF=1)
TIMER2 (TCF=1)
ESAI_1 Receive Data (RDF=1)
ESAI_1 Transmit Data (TDE=1)
Reserved
Reserved
Reserved
DSP56374 Users Guide, Rev. 1.2
Requesting Device
PLL Initialization
4-5