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14.9.2
User Initialization (Prior to Asserting ETHER_EN)
The user needs to initialize portions of the FEC prior to setting the ETHER_EN bit. The exact values depend on the particular application; the
sequence of writing the registers is not important. Ethernet MAC registers requiring initialization are defined in
14.9.2.1
Microcontroller Initialization
In the FEC the descriptor control RISC initializes some registers after ETHER_EN is asserted. After the microcontroller initialization
sequence is complete, hardware is ready for operation.
Table 14-42
shows RISC initialization operations common to the FEC.
14.9.3
Frame Control/Status Words
In the FEC transmit frame control words and receive frame status words cross the following the end of frame data. These words are marked
with a type value of 10 and have the following formats.
14.9.3.1
Receive Frame Status Word
Table 14-2
below defines the format for the receive frame status word.
0
1
2
0
0
0
16
17
18
0
0
0
Bits 31-28, 26-25, 19 and 15-11—Reserved
Freescale Semiconductor
Table 14-41. User Initialization (Before ETHER_EN)
Description
Initialize IMASK
Clear IEVENT (write FFFF_FFFF)
X_WMRK (optional)
IADDR2/IADDR1
GADDR1/GADDR2
PADDR1/PADDR2
OP_PAUSE (only needed for FDX flow control)
MII_SPEED (optional)
Clear MIB_RAM (locations 200–2FC)
Table 14-42. Microcontroller Initialization (FEC)
Description
Initialize BackOff random number seed
Activate Receiver
Activate Transmit
Table 14-43. Receive Frame Status Word Format
3
4
5
6
0
1
0
0
(Last)
19
20
21
22
0
0
MPC5200B Users Guide, Rev. 1
R_CNTRL
X_CNTRL
7
8
9
10
0
BC
MC
LG
23
24
25
26
FRAME_LENGTH
Initialization Sequence
Table
14-41.
11
12
13
14
NO
0
CR
OV
27
28
29
30
15
TR
31
14-35
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