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Table 19-32. User Initialization (Before ECR[ETHER_EN]) (continued)
Table 19-33
defines FEC FIFO/DMA registers that require initialization.
Table 19-33. FEC User Initialization (Before ECR[ETHER_EN])
19.5.4
Microcontroller Initialization
In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted.
After the microcontroller initialization sequence is complete, hardware is ready for operation.
Table 19-34
shows microcontroller initialization operations.
Freescale Semiconductor
Description
PALR / PAUR (only needed for full duplex flow control)
OPD (only needed for full duplex flow control)
RCR
TCR
MSCR (optional)
Clear MIB_RAM
Description
Initialize FRSR (optional)
Initialize EMRBR
Initialize ERDSR
Initialize ETDSR
Initialize (Empty) Transmit Descriptor ring
Initialize (Empty) Receive Descriptor ring
Table 19-34. Microcontroller Initialization
Description
Initialize BackOff Random Number Seed
Activate Receiver
Activate Transmitter
Clear Transmit FIFO
Clear Receive FIFO
Initialize Transmit Ring Pointer
Initialize Receive Ring Pointer
Initialize FIFO Count Registers
MCF5329 Reference Manual, Rev 3
Fast Ethernet Controller (FEC)
19-31
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