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PCI External Signals
10.1.2
Block Diagram
10.2
PCI External Signals
Signal
AD[31:0]
PCI_CBE[3:0]
PCI_DEVSEL
PCI_FRAME
PCI_IDSEL
PCI_IRDY
PCI_PAR
PCI_CLK
PCI_PERR
PCI_RST
PCI_SERR
PCI_STOP
PCI_TRDY
10-2
PCI Controller Block
Config
Master bus
Target
Master
bus/ Com-
mBus
Initiator
Figure 10-1. PCI Block Diagram
Table 10-1. PCI External Signals
I/O
I/O
Multiplexed Address and Data Bus (Shared with ATA and LPC). AD31 is the most
significant bit while AD0 is the least significant as per the PCI specification. The entire
PCI external bus is little Endian ordered.
I/O
Command/Bytes Enables
I/O
Device Select
I/O
Frame
I
Initialization Device Select
I/O
Initiator Ready
I/O
Parity
O
PCI Clock
I/O
Parity Error
O
PCI Reset
I/O
System Error
I/O
Stop
I/O
Target Ready
MPC5200B Users Guide, Rev. 1
PCI
External REQ/GNT
Arbiter
Req/Gnt
PCI
Controller
Config
Interface
Target
Interface
Initiator
Interface
Definition
External
PCI bus
Freescale Semiconductor
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