Functional Description; External Signals (Sdram Side) - Freescale Semiconductor MPC5200B User Manual

8.4

Functional Description

8.4.1

External Signals (SDRAM Side)

Signal Name
MEM_CLK
MEM_CLK
MEM_CLK_EN
MEM_CS[0],
MEM_CS[1]
MEM_RAS
MEM_CAS
MEM_WE
MEM_MA[12:0]
MEM_MBA[1:0]
MEM_DQM[3:0]
MEM_MDQ[31:0]
MEM_MDQS[3:0]
Note: Signals MEM_RAS, MEM_CAS, MEM_WE, and MEM_CLK_EN encode the SDRAM commands to control the
different SDRAM operations.
Note: For 16-bit mode external pull-down devices are required on MEM_MDQS[1:0].
Freescale Semiconductor
Table 8-3. SDRAM External Signals
Outputs
Memory Clock (frequency is the same as the internal XL bus clock). Maximum allowed
value is 132 MHz.
Inverted Memory Clock, used for DDR-SDRAM devices.
Internally generated "DQS" for SDR-SDRAM devices.
Memory Clock Enable (CKE). When low, the SDRAM is disabled. Used to switch memory
into and out of self-refresh/power-down modes.
Memory Command Select. Each space has a command select to enable commands
Memory Row Address Select
Memory Column Address Select
Memory Write Enable
Memory Multiplexed Address. These are used as row address, column address, or
Mode(Extended Mode) register data, depending on the command issued.
Row address during Active command.
Column address during Read and Write commands. MEM_MA10 is used as a control
signal instead of an address line, to control Auto Precharge operation. The Auto Precharge
control bit is not counted as a column address bit. The Memory Controller does not use
Auto Precharge.
Mode register data during Load Mode Register and Load Extended Mode Register (DDR
only) commands.
Memory Bank Address, or Mode register select, depending on the command issued.
Bank address during Precharge Selected, Active, Read, and Write commands. The
Memory Controller does not use the Precharge Selected command.
Mode register select during Load Mode Register and Load Extended Mode Register (DDR
only) commands. Although SDR memory only has a single internal Mode register, the Bank
Address bits must still be valid.
Memory Data Mask. Addressing = 0:3
0 Data byte read/write is enabled
1 Data byte read/write is inhibited
SDR memories 3-state inhibited data during reads; DDR memories ignore Data Mask
during reads. The memory controller never masks read data.
Bidirectional Signals
Memory Data. Addressing = 0:3.
Memory Data Strobe, DDR only. Addressing = 0:3.
MPC5200B Users Guide, Rev. 1
Description
Functional Description
8-15