Program Trace Functional Description - Freescale Semiconductor MPC850 User Manual

Tracking Program Flow
using this information to reconstruct which instructions actually reach retirement.
Instructions are fetched sequentially until branches (direct or indirect), exceptions or
interrupts appear in the program flow or until a stall in execution forces the machine to
avoid fetching the next address. These instructions may be architecturally executed or they
may be canceled in some stage of the machine pipeline.
The information required to enable reconstruction of program trace includes:
• A description of the last fetched instruction (stall, sequential, branch not taken,
branch direct taken, branch indirect taken, interrupt/exception taken).
• The addresses of the targets of all indirect flow changes. Indirect flow changes
include all branches using the link and count registers as the target address, all
interrupts/exceptions, and rfi and mtmsr (because they may cause context
switches).
• The number of instructions canceled on each clock.
The following sections define how this information is generated and how it should be used
to reconstruct the program trace.

44.1.1 Program Trace Functional Description

To make the events that occur in the machine visible, a few dedicated pins are used. Also,
a special bus cycle attribute called program trace cycle is defined. The program trace cycle
attribute is attached to all fetch cycles resulting from indirect flow changes. When program
trace recording is required, the user can ensure these cycles are visible on the external bus.
The core can be forced to show all fetch cycles marked with the program trace cycle
attribute either by setting TECR[VSYNC] of the development port or by programming
ISCT_SER in the instruction support control register (ICTRL). For more information on
VSYNC see Section 44.3.2, "Development Port Communication." Both states described
here are subsequently referred to as VSYNC state.
The VSYNC state forces all fetch cycles marked with the program trace cycle attribute to
be visible on the external bus, even if their data is found in one of the internal devices. To
enable the external hardware to properly synchronize with the internal activity of the core,
entering VSYNC state forces the machine to synchronize and the first fetch after this
synchronization to be marked as a program trace cycle and be seen on the external bus.
In VSYNC state, fetch cycles marked with the program trace cycle attribute become visible
on the external bus. These cycles generate regular bus cycles when the instructions reside
in an external device or generate address-only cycles when instructions are in internal
devices (I-cache and internal memory). In VSYNC state, performance degrades because of
the additional external bus cycles. However, this degradation is very small.
Note that program trace functions are not available when operating the MPC850 in
half-speed bus mode (when SCCR[EBDF] = 0b01). The VFLS[0–1] signals are not valid
in half-speed bus mode.
MPC850 Family User's Manual