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Bits
BCC
Base Class Code
7–0
This field is hard-wired internally as 0x06.
15.2.2.9 Cache Line Size Configuration Register (CLSCR)
CLSCR
Bit
7
6
Type
Reset
0
0
Table 15-13 shows the bit settings of the CLSCR.
Bits
CLS
Cache Line Size
7–0
This field represents the cache-line size of the system in terms of 32-bit words. Although the register is
writable, only the value 0x08 is legal.
15.2.2.10 Latency Timer Configuration Register (LTCR)
LTCR
Bit
7
6
Type
Reset
0
0
Table 15-14 shows the bit settings of the LTCR.
Bits
LT
Latency Timer
7–3
This field specifies, with a granularity of 8 PCI clocks, the length of time that the VCOP, when initiating a
transaction, may hold the bus as the result of a bus grant. Refer to the PCI 2.2 specification for the rules by
which the VCOP completes transactions when the timer has expired.
—
Reserved. Write to 0 for future compatibility. The field is hard-wired to 0 internally
2–0
Freescale Semiconductor
Table 15-12. BCCCR Field Descriptions
Cache Line Size Configuration Register
5
4
CLS
R/W
0
0
Table 15-13. CLSCR Field Descriptions
Latency Timer Configuration Register
5
4
LT
R/W
0
0
Table 15-14. LTCR Field Descriptions
MSC8144E Reference Manual, Rev. 3
Description
3
2
0
0
Description
3
2
0
0
Description
Programming Model
Offset 0x0C
1
0
0
0
Offset 0x0D
1
0
—
R
0
0
15-27
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