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— Accessible to non-core bus masters (e.g. DMA, USB OTG, and LCD controller) via the
crossbar switch
•
8 Kbyte unified cache configurable as instruction-only, data-only, or split I-/D-cache
1.3.3
Phase Locked Loop (PLL)
•
16–66.66 MHz reference crystal
•
Loss-of-lock detection
1.3.4
Power Management
•
Fully static operation with processor sleep and whole chip stop modes
•
Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
•
Peripheral power management register to enable/disable clocks to most modules
•
Software controlled disable of external clock input for low power consumption
1.3.5
Chip Configuration Module (CCM)
•
System configuration during reset
•
Bus monitor
•
Configurable output pad drive strength control
•
Unique part identification and part revision numbers
•
Serial boot capability
— Supports SPI-compatible EEPROM, flash, and FRAM
— Configurable boot clock frequency
1.3.6
Reset Controller
•
Separate reset in and reset out signals
•
Six sources of reset: power-on reset (POR), external, software, watchdog timer, loss of lock, JTAG
instruction
•
Status flag indication of source of last reset
1.3.7
System Control Module
•
Access control registers
•
Core watchdog timer with a 2
•
Core fault reporting
1.3.8
Crossbar Switch Module
•
Concurrent access from different masters to different slaves
Freescale Semiconductor
n
(where n = 8–31) clock cycle selectable timeout period
MCF52277 Reference Manual, Rev. 1
Overview
1-5
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