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11.8.2 Controlling the TLB Replacement Counter
The TLB replacement counter can be programmed to only select among the first six entries
in each translation lookaside buffer by setting the RSV2I bit in the MI_CTR or the RSV2D
bit in the MD_CTR. These control bits also affect the tlbia instruction. Replacement counters
are cleared to zero after execution of the tlbia instruction and the counters decrement after
an appropriate TLB reload.
11.8.3 Invalidating the Translation Lookaside Buffer
The MPC823 implements the tlbie instruction to invalidate the TLB entries. This instruction
invalidates TLB entries in the translation lookaside buffer that hits, including the reserved
entries. Notice that with 4K page size, the 22 most-significant bits of the effective address
are used in the comparison because no segment registers are implemented. Although, for
entries with larger page sizes than 4K, some of the lower bits of the effective page number
are ignored. The ASID value in the entry is ignored for the purpose of matching an
invalidated address, thus multiple entries can be invalidated if they have the same effective
address and different ASID values.
The MPC823 supports the tlbia instruction to invalidate all entries in both translation
lookaside buffers. If the RSV2D or RSV2I bit is set for a translation lookaside buffer, the two
reserved entries will not be invalidated when tlbia is executed. However, the software can
explicitly invalidate one or more of these entries by setting the xTLB_INDX field in the
MD_CTR or MI_CTR, which negates the EV bit in the MD_EPN or MI_EPN register and
performs a write to the appropriate MD_RPN or MI_RPN register. The translation lookaside
buffers are not automatically invalidated on reset, but they are disabled. However, they must
be invalidated under program control.
11.8.4 Loading the Reserved TLB Entries
To load a single reserved entry in the translation lookaside buffer, follow these steps:
1. Disable the translation lookaside buffer by clearing MSR
2. Clear the RSV2x bit in the Mx_CTR.
3. Invalidate the effective address of the reserved page by using the tlbia or tlbie
instruction.
4. Set the xTLB_INDX fields of the Mx_CTR to the appropriate value (6 or 7).
5. Load the Mx_EPN register with the effective page number, the ASID with the reserved
page, and set the EV bit to 1.
6. Run software tablewalk code to load the appropriate entry into the translation
lookaside buffer. Refer to Section 11.8.1.1 Translation Reload Examples for
examples of this code.
7. If needed, repeat the three previous steps to load other TLB entries.
8. Set the RSV2x bit in the Mx_CTR.
Freescale Semiconductor, Inc.
MPC823 REFERENCE MANUAL
For More Information On This Product,
Go to: www.freescale.com
Memory Management Unit
or MSR
as needed.
IR
DR
11-51
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