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CC11x1-Q1
SWRS076B – 11-07-22-013 - APRIL 2009 – REVISED APRIL 2010
3.6
4-Wire Serial Configuration and Data Interface
CC11x1-Q1 is configured via a simple 4-wire SPI-compatible interface (SI, SO, SCLK, and CS) where
CC11x1-Q1 is the slave. This interface is also used to read and write buffered data. All transfers on the
SPI interface are done most significant bit first.
All transactions on the SPI interface start with a header byte containing a R/W bit, a burst access bit (B),
and a 6-bit address (A
The CS pin must be kept low during transfers on the SPI bus. If CS goes high during the transfer of a
header byte or during read/write from/to a register, the transfer is canceled. The timing for the address and
data transfer on the SPI interface is shown in
When CS is pulled low, the MCU must wait until CC11x1-Q1 SO pin goes low before starting to transfer
the header byte. This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF
states, the SO pin goes low immediately after taking CS low.
24
Detailed Description
Figure 3-5. SmartRF Studio User Interface
to A
).
5
0
Figure 3-6
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2.15.
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