Renesas F-ZTAT HD64F3052BF Manuals

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Renesas F-ZTAT HD64F3052BF Hardware Manual (845 pages)

Brand: Renesas | Category: Computer Hardware | Size: 5 MB

Table of Contents
15
Section 1 Overview

29
- Overview
  29
- Block Diagram
  34
- Pin Description
  35
  - Pin Arrangement
    35
  - Pin Assignments in each Mode
    36
  - Pin Functions
    41
Section 2 CPU

47
- Overview
  47
  - Features
    47
  - Differences from H8/300 CPU
    48
- CPU Operating Modes
  49
- Address Space
  50
- Register Configuration
  51
  - Overview
    51
  - General Registers
    52
  - Control Registers
    53
  - Initial CPU Register Values
    54
- Data Formats
  55
  - General Register Data Formats
    55
  - Memory Data Formats
    57
- Instruction Set
  58
- Addressing Modes and Effective Address Calculation
  72
  - Addressing Modes
    72
  - Effective Address Calculation
    75
- Processing States
  79
  - Overview
    79
  - Program Execution State
    80
  - Exception-Handling State
    80
  - Exception-Handling Sequences
    82
  - Bus-Released State
    83
  - Reset State
    83
  - Power-Down State
    83
- Basic Operational Timing
  84
Section 3 MCU Operating Modes

87
- Overview
  87
  - Operating Mode Selection
    87
  - Register Configuration
    88
- Mode Control Register (MDCR)
  88
- System Control Register (SYSCR)
  89
- Operating Mode Descriptions
  91
  - Mode 1
    91
  - Mode 2
    91
  - Mode 3
    91
  - Mode 4
    91
  - Mode 5
    91
  - Mode 6
    92
  - Mode 7
    92
- Pin Functions in each Operating Mode
  92
- Memory Map in each Operating Mode
  93
Section 4 Exception Handling

97
- Overview
  97
- Reset
  100
  - Overview
    100
  - Reset Sequence
    100
  - Interrupts after Reset
    103
- Interrupts
  104
- Trap Instruction
  105
- Stack Status after Exception Handling
  105
- Notes on Use of the Stack
  106
Section 5 Interrupt Controller

107
- Overview
  107
  - Features
    107
  - Block Diagram
    108
  - Pin Configuration
    109
  - Register Configuration
    109
- Register Descriptions
  110
- Interrupt Sources
  120
  - External Interrupts
    120
  - Internal Interrupts
    121
  - Interrupt Exception Vector Table
    121
- Interrupt Operation
  125
  - Interrupt Handling Process
    125
  - Interrupt Exception Handling Sequence
    130
  - Interrupt Response Time
    131
- Usage Notes
  132
Section 6 Bus Controller

137
- Overview
  137
  - Features
    137
  - Block Diagram
    138
  - Pin Configuration
    139
  - Register Configuration
    140
- Register Descriptions
  140
- Operation
  147
  - Area Division
    147
  - Chip Select Signals
    149
  - Data Bus
    150
  - Bus Control Signal Timing
    151
  - Wait Modes
    159
  - Interconnections with Memory (Example)
    165
  - Bus Arbiter Operation
    167
- Usage Notes
  170
  - Connection to Dynamic RAM and Pseudo-Static RAM
    170
  - Register Write Timing
    170
  - BREQ Input Timing
    172
  - Transition to Software Standby Mode
    172
Section 7 Refresh Controller

173
- Overview
  173
  - Features
    173
  - Block Diagram
    175
  - Pin Configuration
    176
  - Register Configuration
    176
- Register Descriptions
  177
- Operation
  183
  - Overview
    183
  - DRAM Refresh Control
    185
  - Pseudo-Static RAM Refresh Control
    200
  - Interval Timer
    204
- Interrupt Source
  210
- Usage Notes
  210
Section 8 DMA Controller

213
- Overview
  213
  - Features
    213
  - Block Diagram
    214
  - Functional Overview
    215
  - Pin Configuration
    217
  - Register Configuration
    217
- Register Descriptions (Short Address Mode)
  219
- Register Descriptions (Full Address Mode)
  226
- Operation
  234
  - Overview
    234
  - I/O Mode
    236
  - Idle Mode
    238
  - Repeat Mode
    241
  - Normal Mode
    245
  - Block Transfer Mode
    248
  - DMAC Activation
    253
  - DMAC Bus Cycle
    255
  - DMAC Multiple-Channel Operation
    261
  - External Bus Requests, Refresh Controller, and DMAC
    262
  - NMI Interrupts and DMAC
    263
  - Aborting a DMA Transfer
    264
  - Exiting Full Address Mode
    265
  - DMAC States in Reset State, Standby Modes, and Sleep Mode
    266
- Interrupts
  267
- Usage Notes
  268
Section 9 I/O Ports

273
- Overview
  273
- Port 1
  277
  - Overview
    277
  - Overview
    280
  - Register Configuration
    281
- Port 3
  284
  - Overview
    284
- Port 4
  286
  - Overview
    286
- Port 5
  290
  - Overview
    290
- Port 6
  294
  - Overview
    294
  - Register Configuration
    295
- Port 7
  298
  - Overview
    298
  - Register Configuration
    299
- Port 8
  300
  - Overview
    300
  - Register Configuration
    301
- Port 9
  305
  - Overview
    305
  - Register Configuration
    306
- Port a
  309
  - Overview
    309
  - Register Configuration
    311
  - Pin Functions
    313
- Port B
  321
  - Overview
    321
  - Register Configuration
    323
  - Pin Functions
    325
Section 10 16-Bit Integrated Timer Unit (ITU)

331
- Overview
  331
  - Features
    331
  - Block Diagrams
    334
  - Pin Configuration
    339
  - Register Configuration
    340
- Register Descriptions
  343
  - Timer Start Register (TSTR)
    343
  - Timer Synchro Register (TSNC)
    344
  - Timer Mode Register (TMDR)
    346
  - Timer Function Control Register (TFCR)
    349
  - Timer Output Master Enable Register (TOER)
    351
  - Timer Output Control Register (TOCR)
    353
  - Timer Counters (TCNT)
    354
  - General Registers (GRA, GRB)
    355
  - Buffer Registers (BRA, BRB)
    356
  - Timer Control Registers (TCR)
    357
  - Timer I/O Control Register (TIOR)
    359
  - Timer Status Register (TSR)
    361
  - Timer Interrupt Enable Register (TIER)
    363
- CPU Interface
  365
  - 16-Bit Accessible Registers
    365
  - 8-Bit Accessible Registers
    367
- Operation
  368
  - Overview
    368
  - Basic Functions
    369
  - Synchronization
    378
  - PWM Mode
    379
  - Reset-Synchronized PWM Mode
    383
  - Complementary PWM Mode
    386
  - Phase Counting Mode
    395
  - Buffering
    397
  - ITU Output Timing
    404
- Interrupts
  406
- Usage Notes
  410
Section 11 Programmable Timing Pattern Controller

425
- Overview
  425
  - Features
    425
  - Block Diagram
    426
  - Pin Configuration
    427
  - Register Configuration
    428
- Register Descriptions
  429
  - Port a Data Direction Register (PADDR)
    429
  - Port a Data Register (PADR)
    429
  - Port B Data Direction Register (PBDDR)
    430
  - Port B Data Register (PBDR)
    430
  - Next Data Register a (NDRA)
    431
  - Next Data Register B (NDRB)
    433
  - Next Data Enable Register a (NDERA)
    435
  - Next Data Enable Register B (NDERB)
    436
  - TPC Output Control Register (TPCR)
    437
  - TPC Output Mode Register (TPMR)
    439
- Operation
  441
  - Overview
    441
  - Output Timing
    442
  - Normal TPC Output
    443
  - Non-Overlapping TPC Output
    445
  - TPC Output Triggering by Input Capture
    447
- Usage Notes
  448
  - Operation of TPC Output Pins
    448
  - Note on Non-Overlapping Output
    448
Section 12 Watchdog Timer

451
- Overview
  451
  - Features
    451
  - Block Diagram
    452
  - Register Configuration
    452
- Register Descriptions
  453
  - Timer Counter (TCNT)
    453
  - Timer Control/Status Register (TCSR)
    454
  - Reset Control/Status Register (RSTCSR)
    456
  - Notes on Register Access
    457
- Operation
  458
- Interrupts
  462
- Usage Notes
  462
Section 13 Serial Communication Interface

463
- Overview
  463
  - Features
    463
  - Block Diagram
    465
  - Pin Configuration
    466
  - Register Configuration
    466
- Register Descriptions
  467
  - Receive Shift Register (RSR)
    467
  - Receive Data Register (RDR)
    467
  - Transmit Shift Register (TSR)
    468
  - Transmit Data Register (TDR)
    468
  - Serial Mode Register (SMR)
    469
  - Serial Control Register (SCR)
    472
  - Serial Status Register (SSR)
    476
  - Bit Rate Register (BRR)
    480
- Operation
  490
  - Overview
    490
  - Operation in Asynchronous Mode
    492
  - Multiprocessor Communication
    501
  - Synchronous Operation
    508
- SCI Interrupts
  516
- Usage Notes
  517
Section 14 Smart Card Interface

523
- Overview
  523
  - Features
    523
  - Block Diagram
    524
  - Pin Configuration
    525
  - Register Configuration
    525
- Register Descriptions
  526
  - Smart Card Mode Register (SCMR)
    526
  - Serial Status Register (SSR)
    527
  - Serial Mode Register (SMR)
    529
  - Serial Control Register (SCR)
    530
- Operation
  531
  - Overview
    531
  - Pin Connections
    531
  - Data Format
    533
  - Register Settings
    534
  - Clock
    536
  - Transmitting and Receiving Data
    538
- Usage Notes
  545
Section 15 A/D Converter

549
- Overview
  549
  - Features
    549
  - Block Diagram
    550
  - Pin Configuration
    551
  - Register Configuration
    552
- Register Descriptions
  553
- CPU Interface
  557
- Operation
  558
  - Single Mode (SCAN = 0)
    558
  - Scan Mode (SCAN = 1)
    560
  - Input Sampling and A/D Conversion Time
    562
  - External Trigger Input Timing
    563
- Interrupts
  564
- Usage Notes
  564
Section 16 D/A Converter

571
- Overview
  571
  - Features
    571
  - Block Diagram
    572
  - Pin Configuration
    573
  - Register Configuration
    573
- Register Descriptions
  574
- Operation
  577
- D/A Output Control
  578
Section 17 RAM

579
- Overview
  579
  - Block Diagram
    580
  - Register Configuration
    581
- System Control Register (SYSCR)
  581
- Operation
  582
Section 18 ROM

583
- Features
  583
- Overview
  584
  - Block Diagram
    584
  - Mode Transitions
    584
  - On-Board Programming Modes
    587
  - Flash Memory Emulation in RAM
    589
  - Differences between Boot Mode and User Program Mode
    590
  - Block Configuration
    591
- Pin Configuration
  592
- Register Configuration
  592
- Register Descriptions
  593
- On-Board Programming Modes
  602
  - Boot Mode
    602
  - User Program Mode
    608
- Programming/Erasing Flash Memory
  610
  - Program Mode
    612
  - Program-Verify Mode
    613
  - Notes on Program/Program-Verify Procedure
    613
  - Erase Mode
    617
  - Erase-Verify Mode
    617
- Protection
  619
  - Hardware Protection
    619
  - Software Protection
    621
  - Error Protection
    622
  - NMI Input Disable Conditions
    623
- Flash Memory Emulation in RAM
  625
- Flash Memory PROM Mode
  627
  - 18.10.1 Socket Adapters and Memory Map
    627
  - 18.10.2 Notes on Use of PROM Mode
    628
- Notes on Flash Memory Programming/Erasing
  629
Section 19 Clock Pulse Generator

635
- Overview
  635
  - Block Diagram
    636
- Oscillator Circuit
  637
  - Connecting a Crystal Resonator
    637
  - External Clock Input
    639
- Duty Adjustment Circuit
  641
- Prescalers
  641
- Frequency Divider
  641
  - Register Configuration
    642
  - Division Control Register DIVCR
    642
  - Usage Notes
    643
Section 20 Power-Down State

645
- Overview
  645
- Register Configuration
  647
  - System Control Register (SYSCR)
    647
  - Module Standby Control Register (MSTCR)
    649
- Sleep Mode
  651
  - Transition to Sleep Mode
    651
  - Exit from Sleep Mode
    651
- Software Standby Mode
  652
- Hardware Standby Mode
  656
- Module Standby Function
  657
  - Module Standby Timing
    657
  - Read/Write in Module Standby
    657
  - Usage Notes
    657
- System Clock Output Disabling Function
  658
Section 21 Electrical Characteristics

659
- Absolute Maximum Ratings
  659
- Electrical Characteristics
  660
  - DC Characteristics
    660
  - AC Characteristics
    664
  - A/D Conversion Characteristics
    668
  - D/A Conversion Characteristics
    669
  - Flash Memory Characteristics
    670
- Operational Timing
  671
  - Bus Timing
    671
  - Refresh Controller Bus Timing
    675
  - Control Signal Timing
    680
  - Clock Timing
    682
  - TPC and I/O Port Timing
    682
  - ITU Timing
    683
  - SCI Input/Output Timing
    684
  - DMAC Timing
    685
Appendix A Instruction Set

687
- Instruction List
  687
- Operation Code Map
  702
- Number of States Required for Execution
  705
Appendix B Internal I/O Register

715
- Addresses
  715
- Function
  723
- B.2 Function
  723
Appendix C I/O Port Block Diagrams

804
- Port 1 Block Diagram
  804
- Port 2 Block Diagram
  805
- Port 3 Block Diagram
  806
- Port 4 Block Diagram
  807
- Port 5 Block Diagram
  808
- Port 6 Block Diagrams
  809
- Port 7 Block Diagrams
  813
- Port 8 Block Diagrams
  814
- Port 9 Block Diagrams
  817
- Port a Block Diagrams
  821
- Port B Block Diagrams
  825
Appendix D Pin States

829
- Port States in each Mode
  829
- Pin States at Reset
  832
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

835
- Timing of Transition to Hardware Standby Mode
  835
Appendix F Product Code Lineup

836
Appendix G Package Dimensions

837
Appendix H Differences from H8/3048F-ZTAT

839

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Renesas F-ZTAT HD64F3052BF Manuals

Renesas F-ZTAT HD64F3052BF Hardware Manual (845 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller

Section 7 Refresh Controller

Section 8 DMA Controller

Section 9 I/O Ports

Section 10 16-Bit Integrated Timer Unit (ITU)

Section 11 Programmable Timing Pattern Controller

Section 12 Watchdog Timer

Section 13 Serial Communication Interface

Section 14 Smart Card Interface

Section 15 A/D Converter

Section 16 D/A Converter

Section 17 RAM

Section 18 ROM

Section 19 Clock Pulse Generator

Section 20 Power-Down State

Section 21 Electrical Characteristics

Appendix A Instruction Set

Appendix B Internal I/O Register

Appendix C I/O Port Block Diagrams

Appendix D Pin States

Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

Appendix F Product Code Lineup

Appendix G Package Dimensions

Appendix H Differences from H8/3048F-ZTAT

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