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Field
15–10
Specifies the command. These values are listed in
Operation
9
Reserved, must be cleared.
8
Direction of operand transfer.
R/W
0 Data is written to the CPU or to memory from the development system.
1 The transfer is from the CPU to the development system.
7–6
Operand Data Size for Sized Operations. Addresses are expressed as 32-bit absolute values. A command
Op Size
performing a byte-sized memory read leaves the upper 8 bits of the response data undefined. Referenced data is
returned in the lower 8 bits of the response.
5–4
Reserved, must be cleared.
3
Address/Data. Determines whether the register field specifies a data or address register.
A/D
0 Data register.
1 Address register.
2–0
Contains the register number in commands that operate on processor registers. See
Register
36.4.1.3.3
Extension Words as Required
Some commands require extension words for addresses and/or immediate data. Addresses require two
extension words because only absolute long addressing is permitted. Longword accesses are forcibly
longword-aligned and word accesses are forcibly word-aligned. Immediate data can be 1 or 2 words long.
Byte and word data each requires a single extension word, while longword data requires two extension
words.
Operands and addresses are transferred most-significant word first. In the following descriptions of the
BDM command set, the optional set of extension words is defined as address, data, or operand data.
36.4.1.4
Command Sequence Diagrams
The command sequence diagram in
represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system
sends to the debug module; the bottom half indicates the debug module's response to the previous
development system commands. Command and result transactions overlap to minimize latency.
Freescale Semiconductor
Table 36-19. BDM Field Descriptions
Description
Table
36-20.
Operand Size
00
Byte
01
Word
10
Longword
11
Reserved
Figure 36-16
shows serial bus traffic for commands. Each bubble
MCF5329 Reference Manual, Rev 3
Bit Values
8 bits
16 bits
32 bits
—
Table
36-21.
Debug Module
36-21
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