Bus Commands - Freescale Semiconductor MSC8144E Reference Manual

Mode
Target only PCICCR[BMST] = 0
PCICR[MEM] = 1
C2GPR[PMDRD] = 0
C2GPR[PPE] = 0
Initiator and PCICCR[BMST] = 1
target PCICR[MEM] = 1
C2GPR[PMDRD] = 0
C2GPR[PPE] = 0

15.1.2 Bus Commands

PCI bus commands indicate the type of transaction occurring on the bus. These commands are
encoded on
PCI_C/BE[3–0]
described in Table 15-2.
PCI_C/
Command Type
BE[3–0]
Interrupt 0b0000
acknowledge
Special cycle 0b0001
I/O read 0b0010
I/O write 0b0011
— 0b010x
Memory read 0b0110
Memory write 0b0111
— 0b100x
Configuration read 0b1010
Configuration write 0b1011
Memory read 0b1100
multiple
Dual address cycle 0b1101
Memory read line 0b1110
Memory write and 0b1111
invalidate
Note: As an initiator, 32-byte burst reads are translated either to a memory read line or
memory read multiple depending on the configuration of C2GPR[PRCS] (see Chapter
4, Chip-Level Arbitration and Switching System (CLASS)).
Freescale Semiconductor
Table 15-1. PCI Operation Modes (Continued)
Settings
No master is allowed to initiate transactions toward the PCI, the PCI
master delayed read must be enabled, and the controller internal
pipeline must be disabled.
• The four DSP cores, the DMA controller, or the QUICC Engine
subsystem can initiate transactions toward PCI.
• The serial RapidIO controller and TDM modules must not initiate
PCI transactions
• The PCI master delayed read must be enabled.
• The internal PCI controller pipeline must be disabled.
during the address phase of the transaction. PCI bus commands are
Table 15-2. PCI Command Definitions
A read implicitly addressed to the system interrupt
controller. The size of the vector to be returned is
indicated on the byte enables after the address phrase.
Provides a simple message broadcast mechanism.
Accesses agents mapped in I/O address space.
Accesses agents mapped in I/O address space.
Reserved. No response occurs.
Accesses agents mapped in memory address space. A
read from prefetchable space, when seen as a target,
fetches a cache line of data (32 bytes) from the starting
address, even though all 32 bytes may not actually be
sent to the initiator.
Accesses agents mapped in memory address space.
Reserved. No response occurs.
Accesses the PCI configuration space.
Accesses the PCI configuration space.
Causes a prefetch of the next cache line.
Transfers an 8-byte address to devices.
Indicates that the initiator intends to transfer an entire
cache line of data.
Indicates that the initiator will transfer an entire cache
line of data, and if PCI has any cacheable memory, this
line needs to be invalidated.
MSC8144E Reference Manual, Rev. 3
Description
Definition
Functional Description
Supported as:
Initiator Target
Yes No
Yes No
Yes No
Yes No
— —
Yes Yes
Yes Yes
— —
No Yes
No Yes
Yes Yes
No Yes
Yes Yes
No Yes
15-3