Pci Bus Commands - Freescale Semiconductor MCF5480 Reference Manual

0
PCI_CLK
FRAME
PCIAD
PCICXBE
PCIIRDY
PCITRDY
DEVSEL
PCISTOP

19.4.1.4 PCI Bus Commands

PCI supports a number of different commands. These commands are presented by the initiator on the
PCICXBE[3:0] lines during the address phase of a PCI transaction.
PCI Bus
PCICXBE[3:0]
Command
0000 Interrupt
Acknowledge
0001 Special Cycle
0010 I/O read
0011 I/O write
0100 Reserved
0101 Reserved
0110 Memory-read
0111 Memory-write
1000 Reserved
Freescale Semiconductor
1 2 3
A1 D1
CMD BYTE ENABLES
Address Data
Phase Phase 1
Figure 19-48. PCI Write Terminated by Target
Table 19-47. PCI Bus Commands
MCF548x MCF548x
Supports as Supports
Initiator as Target
Yes No
Yes No
Yes No
Yes No
No No
No No
Yes Yes
Yes Yes
No No
MCF548x Reference Manual, Rev. 3
4 5 6
D2
BYTE ENABLES
(Wait)
Data
Phase 2
The interrupt acknowledge command is a read (implicitly
addressing an external interrupt controller). Only one
device on the PCI bus should respond to the interrupt
acknowledge command.
The Special Cycle command provides a mechanism to
broadcast select messages to all devices on the PCI bus.
The I/O read command accesses agents mapped into the
PCI I/O space.
The I/O write command accesses agents mapped into the
PCI I/O space.
The memory read command accesses agents mapped into
PCI memory space.
The memory write command accesses agents mapped into
PCI memory space.
Functional Description
7 8 9
Definition
—
—
—
19-51