Pci Bus Commands; Pci Write Terminated By Target - Freescale Semiconductor MPC5200B User Manual

CLK
FRAME
AD
C/BE
IRDY
TRDY
DEVSEL
STOP
10.4.1.4

PCI Bus Commands

PCI supports a number of different commands. These commands are presented by the initiator on the C/BE[3:0] lines during the address phase
of a PCI transaction.
PCI Bus
C/BE[3:0]
Command
0000 Interrupt
Acknowledge
0001 Special Cycle
0010 I/O-read
0011 I/O-write
0100 Reserved
0101 Reserved
0110 Memory-read
Freescale Semiconductor
1 2 3
A1 D1
CMD Byte Enables
Address Data Phase 1
Phase
Figure 10-3. PCI Write Terminated by Target
Table 10-5. PCI Bus Commands
MPC5200B MPC5200B
supports as supports
Initiator as Target
Yes
Yes
Yes
Yes
No
No
Yes
MPC5200B Users Guide, Rev. 1
4 5
D2
(wait)
Data Phase 2
No The interrupt acknowledge command is a read
(implicitly addressing an external interrupt
controller). Only one device on the PCI bus should
respond to the interrupt acknowledge command.
No The Special Cycle command provides a
mechanism to broadcast select messages to all
devices on the PCI bus.
No The I/O-read command accesses agents mapped
into the PCI I/O space.
No The I/O-write command accesses agents mapped
into the PCI I/O space.
No --
No --
Yes The memory read command accesses agents
mapped into PCI memory space.
Functional Description
6 7
Definition
8
10-47