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Power
Power Name
CORE_VDD (4)
Core Power—The voltage (1.25 V) should be well-regulated, and the input should be provided
with an extremely low impedance path to the 1.25 V
adequate external decoupling capacitors.
IO_VDD
SHI, ESAI, ESAI_1, WDT and Timer I/O Power —The voltage (3.3 V) should be well-regulated,
(80-pin 4)
and the input should be provided with an extremely low impedance path to the 3.3 V
(52-pin 3)
This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must provide
adequate external decoupling capacitors.
IO_Vdd
MODA_IRQA_PH0
MODB_IRQB_PH1
GPIO_PG13
GPIO_PG12
MODC_IRQC_PH2
MODD_IRQD_PH3
GPIO_PG11
Core_Vdd
Core_Gnd
GPIO_PG10
GPIO_PG9
HREQ_PH4
SS_HA2
SCK_SCL
MISO_SDA
MOSI_HA0
GPIO_PG8
GPIO_PG7
IO_Gnd
3.3 V
2-2
Table 2-2. Power Inputs
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Figure 2-1. 80-pin Vdd Connections
DSP56374 Users Guide, Rev. 1.2
power rail. The user must provide
DD
60
SDO5_1_PE6
59
SDO4_1_PE7
58
SDO3_PC8
57
SDO2_PC9
56
SDO1_PC10
55
SDO0_PC11
54
SDO3_1_PE8
53
SDO2_1_PE9
52
Core_Vdd
51
Core_Gnd
50
SDO1_1_PE10
49
SDO0_1_PE11
48
PINIT_NMI
47
IO_Vdd
46
XTAL
45
EXTAL
44
PLLD_Vdd
43
PLLD_Gnd
42
PLLP_Gnd
41
PLLP_Vdd
1.25 V
Filter
Freescale Semiconductor
power rail.
DD
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