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•
Small 1KB sector sizes (minimum erase resolution of 1KB)
•
Up to 100,000 program/erase cycles on the lower 32KB of the flash memory, with up to 10,000 program/
erase cycles on the remaining flash memory (devices with 32KB support 100,000 cycles on the entire flash
memory)
For a complete description of the flash memory, see the NVM chapter of the technical reference manual.
8.9 SRAM
MSPM0Gxx MCUs include a low power, high performance SRAM memory with zero wait state access across
the supported CPU frequency range of the device. MSPM0Gxx MCUs also provides up to 32KB of SRAM with
hardware parity. SRAM memory can be used for storing volatile information such as the call stack, heap, global
data, and code. The SRAM memory content is fully retained in run, sleep, stop, and standby operating modes
and is lost in shutdown mode. A write protection mechanism is provided to allow the application to prevent
unintended modifications to the SRAM memory. Write protection is useful when placing executable code into
SRAM as it provides a level of protection against unintentional overwrites of code by either the CPU or DMA.
Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower
power consumption.
8.10 GPIO
The general purpose input/output (GPIO) peripheral provides the user with a means to write data out and read
data in to and from the device pins. Through the use of the Port A and Port B GPIO peripherals, these devices
support up to 60 GPIO pins.
The key features of the GPIO module include:
•
0 wait state MMR access from CPU
•
Set/Clear/Toggle multiple bits without the need of a read-modify-write construct in software
•
GPIOs with "Standard with Wake" drive functionality able to wake the device from SHUTDOWN mode
•
"FastWake" feature enables low-power wakeup from STOP and STANDBY modes for any GPIO port
•
User controlled input filtering
For more details, see the GPIO chapter of the
Manual.
8.11 IOMUX
The IOMUX peripheral enables IO pad configuration and controls digital data flow to and from the device pins.
The key features of the IOMUX include:
•
IO Pad configuration registers allow for programmable drive strength, speed, pullup-down, and more
•
Digital pin muxing allows for multiple peripheral signals to be routed to the same IO pad
•
Pin functions and capabilities are user-configured using the PINCM register
For more details, see the IOMUX chapter of the
Manual.
8.12 ADC
Both 12-bit analog-to-digital converter (ADC) modules in these devices, ADC0 and ADC1, support fast 12-bit
conversions with single-ended inputs and simultaneous sampling operation.
ADC features include:
•
12-bit output resolution at 4Msps with greater than 11.1 ENOB
•
HW averaging enables 14-bit effective resolution at 250ksps
•
Up to 17 total external input channels with individual result storage registers
•
Internal channels for temperature sensing, supply monitoring, and analog signal chain (interconnection with
OPA, DAC, etc.)
•
Software selectable reference:
Copyright © 2023 Texas Instruments Incorporated
MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
Product Folder Links:
MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
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