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Spartan-6 FPGA Series
Xilinx Spartan-6 FPGA Series Manuals
Manuals and User Guides for Xilinx Spartan-6 FPGA Series. We have
7
Xilinx Spartan-6 FPGA Series manuals available for free PDF download: Design And Pin Planning Manual, User Manual, Getting Started
Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual (72 pages)
Printed circuit boards
Brand:
Xilinx
| Category:
Motherboard
| Size: 10 MB
Table of Contents
Revision History
2
Table of Contents
3
Preface: about this Guide
7
Guide Contents
7
Additional Documentation
7
Additional Support Resources
8
Chapter 1: PCB Technology Basics
9
PCB Structures
9
Traces
9
Planes
9
Vias
10
Pads and Antipads
10
Lands
10
Dimensions
10
Transmission Lines
11
Return Currents
12
Chapter 2: Power Distribution System
13
PCB Decoupling Capacitors
13
Recommended Capacitors Per Device
13
Required PCB Capacitor Quantities
14
Capacitor Specifications
16
PCB Bulk Capacitors
16
PCB High-Frequency Capacitors
16
Capacitor Consolidation Rules
17
PCB Capacitor Placement and Mounting Techniques
17
PCB Bulk Capacitors
17
0805 Ceramic Capacitor
18
0402 Ceramic Capacitor
19
Basic PDS Principles
20
Noise Limits
20
Role of Inductance
22
Capacitor Parasitic Inductance
22
PCB Current Path Inductance
24
Capacitor Mounting Inductance
24
Plane Inductance
25
FPGA Mounting Inductance
26
PCB Stackup and Layer Order
27
Capacitor Effective Frequency
28
Capacitor Anti-Resonance
30
Capacitor Placement Background
30
Vref
31
Power Supply Consolidation
31
Unconnected VCCO Pins
32
Simulation Methods
32
PDS Measurements
33
Noise Magnitude Measurement
33
Noise Spectrum Measurements
35
Optimum Decoupling Network Design
37
Troubleshooting
37
Possibility 1: Excessive Noise from Other Devices on the PCB
37
Possibility 2: Parasitic Inductance of Planes, Vias, or Connecting Traces
37
Possibility 3: I/O Signals in PCB Are Stronger than Necessary
38
Possibility 4: I/O Signal Return Current Traveling in Sub-Optimal Paths
38
Chapter 3: Selectio Signaling
39
Interface Types
39
Single-Ended Versus Differential Interfaces
39
SDR Versus DDR Interfaces
40
Single-Ended Signaling
40
Modes and Attributes
40
Input Thresholds
40
Chapter 4: PCB Materials and Traces
41
How Fast Is Fast
41
Dielectric Losses
41
Relative Permittivity
41
Loss Tangent
42
Skin Effect and Resistive Losses
42
Choosing the Substrate Material
42
Traces
43
Trace Geometry
43
Trace Characteristic Impedance Design for High-Speed Transceivers
43
Trace Routing
45
Plane Splits
45
Return Currents
45
Simulating Lossy Transmission Lines
46
Cable
46
Connectors
46
Skew between Conductors
46
Chapter 5: Design of Transitions for High-Speed Signals
47
Excess Capacitance and Inductance
47
Time Domain Reflectometry
47
BGA Package
49
SMT Pads
49
Differential Vias
53
P/N Crossover Vias
56
SMA Connectors
56
Backplane Connectors
56
Microstrip/Stripline Bends
56
Chapter 6: I/O Pin and Clock Planning
61
Configuration Modes
61
Configuration Pin Planning Considerations
61
Multi-Function Configuration
61
Configuration Options
62
Memory Controller Block
62
MCB Pin Planning Considerations
62
MCB Clocking Considerations
63
Pci
63
GTP Transceivers
63
GTP Transceiver Pin Planning Considerations
63
GTP Transceiver Clocking Considerations
64
PCI Express
64
Other GTP Transceiver Based Tools
64
Global and I/O Clocking
64
GCLK Pin Assignment
64
BUFIO2 I/O Clock Buffer Usage
65
Overview of BUFIO2 Resource Usage Per Interface Type
66
Bidirectional I/O
66
Serializing Interfaces
66
Pin Planning Considerations
66
Single-Ended Serdes
66
Differential Serdes
67
Power Management-Using Suspend/Awake
67
I/O Standards and I/O Banking Rules
67
Simultaneous Switching Output (SSO) Management
67
Running Design Rule Checks
67
Density Migration
68
Appendix A: Recommended PCB Design Rules
69
Recommended PCB Design Rules for QFP Packages
69
Recommended PCB Design Rules for BGA and CSP Packages
70
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Xilinx Spartan-6 FPGA Series User Manual (67 pages)
Brand:
Xilinx
| Category:
Motherboard
| Size: 2 MB
Table of Contents
Revision History
2
Table of Contents
3
Preface: about this Guide
5
Guide Contents
5
Additional Documentation
5
Additional Support Resources
6
Chapter 1: SP605 Evaluation Board
7
Overview
7
Additional Information
7
Features
8
Block Diagram
9
Related Xilinx Documents
10
Detailed Description
10
1 Spartan-6 XC6SLX45T-3FGG484 FPGA
12
Configuration
12
I/O Voltage Rails
13
2 MB DDR3 Component Memory
13
3 SPI X4 Flash
16
4 Linear BPI Flash
18
FPGA Design Considerations for the Configuration Flash
20
5 System ACE CF and Compactflash Connector
20
6 Usb Jtag
22
7 Clock Generation
23
Oscillator (Differential)
23
Oscillator Socket (Single-Ended, 2.5V or 3.3V)
24
SMA Connectors (Differential)
25
8 Multi-Gigabit Transceivers (GTP Mgts)
25
9 PCI Express Endpoint Connectivity
28
10 SFP Module Connector
30
100 /1000 Tri-Speed Ethernet PHY
31
12 USB-To-UART Bridge
33
506 DVI Codec
34
14 IIC Bus
35
8-Kb NV Memory
36
15 Status Leds
38
Ethernet PHY Status Leds
39
FPGA INIT and DONE Leds
40
16 User I/O
41
User Leds
41
User Pushbutton Switches
42
User DIP Switch
43
User SIP Header
44
User SMA GPIO
45
17 Switches
46
Power On/Off Slide Switch SW2
46
FPGA_PROG_B Pushbutton SW3 (Active-Low)
47
SYSACE_RESET_B Pushbutton SW9 (Active-Low)
47
System ACE CF Compactflash Image Select DIP Switch S1 (Active-High)
48
Mode DIP Switch SW1 (Active-High)
49
18 VITA 57.1 FMC LPC Connector
50
Power Management
52
AC Adapter and 12V Input Power Jack/Switch
52
Onboard Power Regulation
53
Configuration Options
55
For more Information
61
Xilinx Spartan-6 FPGA Series User Manual (40 pages)
Brand:
Xilinx
| Category:
Control Unit
| Size: 1 MB
Table of Contents
Revision History
2
Table of Contents
3
Preface: about this Guide
5
Guide Contents
5
Additional Documentation
5
Additional Support Resources
6
Chapter 1: Power Management with Suspend Mode
7
Introduction
7
Differences from Extended Spartan-3A Family
7
Multi-Pin Wake-Up
7
Suspend Synchronization
7
Suspend Features
8
Design Steps
8
Entering Suspend Mode
8
Exiting Suspend Mode
12
PROGRAM_B Programming Pin Always Overrides Suspend Mode
14
Enable the Suspend Feature and Glitch Filtering
14
User Constraints File Enable
14
Bitstream Generator
14
Define the Multi-Pin Wake-Up Feature and Pins
15
Define the I/O Behavior During Suspend Mode
15
Single-Ended I/O Standards
15
Differential I/O Standards
15
SUSPEND Attribute
16
UCF Example
16
Design Maintained During Suspend Mode
16
Design Requirements to Maintain Application Data
17
Suspend Mode Wake-Up Timing Controls
17
Wake-Up Timing Clock Source
17
Switch Outputs from Suspend to Normal Behavior
19
Release Write Protect on Clocked Primitives
19
Dedicated Configuration Pins Unaffected During Suspend Mode
19
JTAG Operations Allowed During Suspend Mode
19
SUSPEND Pin
20
Characteristics
20
SUSPEND Input Glitch Filter
21
SUSPEND_SYNC Primitive
21
AWAKE Pin
21
General Behavior (Suspend Feature Disabled)
21
AWAKE Pin Behavior When Suspend Feature Is Enabled
21
Controlling Wake-Up from an External Source
22
Synchronizing Wake-Up
22
Post-Configuration CRC Limitations When Using Suspend Mode
22
FPGA Voltage Requirements During Suspend Mode
24
Memory Controller Block
24
Chapter 2: Voltage Supplies
26
Vccint
26
Vccaux
26
Setting the VCCAUX Level
27
VCCAUX Specifications
27
Vcco
27
Vref
28
Board Design and Signal Integrity
28
Simultaneously Switching Outputs
28
Power Distribution System Design and Decoupling/Bypass Capacitors
28
Chapter 3: Lower-Power Spartan-6 LX Devices
29
Introduction
29
Designing Using the Lower-Power Spartan-6 LX Devices
29
Lower-Power Spartan-6 LX Device Specifications
30
Chapter 4: Power-On and Power-Down Behavior Including Hibernate
31
Introduction
31
Power-On Reset
31
Supply Sequencing
32
Ramp Rate
32
Hot Swap
32
Configuration Data Retention and Brown out
33
GTP Transceiver Power-Up and Power-Down
33
Hibernate Power down
33
Forcing FPGA to Quiescent Current Levels
34
Entering Hibernate State
34
Turn off VCCO
35
Exiting Hibernate
36
Design Considerations
36
Chapter 5: Power Estimation
37
Introduction
37
Voltage Regulators
37
Saving Power
38
Saving Clock Routing Power
39
ISE Design Suite Power Optimization
39
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Xilinx Spartan-6 FPGA Series User Manual (55 pages)
Brand:
Xilinx
| Category:
Motherboard
| Size: 1 MB
Table of Contents
Revision History
3
Table of Contents
5
Preface: about this Guide
7
Guide Contents
7
Additional Resources
7
Conventions
7
Typographical
7
Online Document
8
Chapter 1: SP601 Evaluation Board
9
Overview
9
Additional Information
9
Features
10
Block Diagram
11
Related Xilinx Documents
11
Detailed Description
12
1 Spartan-6 XC6SLX16-2CSG324 FPGA
13
Configuration
13
I/O Voltage Rails
13
2 MB DDR2 Component Memory
14
3 SPI X4 Flash
18
4 Linear Flash BPI
20
100 /1000 Tri-Speed Ethernet PHY
23
6 USB-To-UART Bridge
25
7 IIC Bus
26
8 Kb NV Memory
27
Clock Generation
27
Oscillator (Differential)
27
Oscillator Socket (Single-Ended, 2.5V or 3.3V)
28
SMA Connectors (Differential)
28
9 VITA 57.1 FMC-LPC Connector
28
10 Status Leds
32
11 FPGA Awake LED and Suspend Jumper
33
12 FPGA INIT and DONE Leds
34
13 User I/O
35
14 FPGA_PROG_B Pushbutton Switch
40
Power Management
40
AC Adapter and 5V Input Power Jack/Switch
40
Onboard Power Supplies
40
Configuration Options
42
JTAG Configuration
42
Xilinx Spartan-6 FPGA Series Getting Started (37 pages)
Brand:
Xilinx
| Category:
Motherboard
| Size: 4 MB
Table of Contents
Revision History
2
Table of Contents
3
Preface: about this Guide
5
Additional Documentation
5
Additional Resources
6
Conventions
6
Typographical
6
Online Document
7
Getting Started with the Spartan-6 FPGA SP605 Embedded Kit
9
Introduction
9
SP605 Embedded Kit Contents
9
What's Inside the Box
9
What's Available Online
10
Getting Started with the Video Demonstration
10
Processor System Used for the Video Demo
10
Video Demo Hardware Requirements
11
Video Demo Hardware Setup Instructions
11
Running the Video Demo
13
Getting Started with the Petalinux Demonstration
14
Processor System Used for the Petalinux Demo
15
Petalinux Demo Hardware Setup Instructions
16
Running the Petalinux Demo
17
Installation and Licensing of ISE Design Suite 12.1
18
ISE 12.1 Software Installation
18
Downloading and Installing Tool Licenses
22
Communicating with the SP605 USB-UART
27
Installing the USB-UART Driver
27
Connecting to the SP605 UART
27
Configuring the Host Computer
27
Testing the USB-UART Driver Installation
29
Next Steps
30
Data Sheet
32
DS757 SP605 Embedded Kit Microblaze Processor Subsystem Data Sheet
32
Tutorials
32
UG729 SP605 Microblaze Processor Subsystem Software Tutorial
32
UG728 SP605 Microblaze Processor Subsystem Hardware Tutorial
32
Reference Designs
32
Microblaze Processor Subsystem
32
Microblaze Processor Subsystem with Video Pipeline Demo
32
Getting Help and Support
33
Appendix A: Warranty
35
Xilinx Spartan-6 FPGA Series Getting Started (32 pages)
Evaluation Kit
Brand:
Xilinx
| Category:
Motherboard
| Size: 26 MB
Table of Contents
Table of Contents
3
Introduction
5
SP605 Evaluation Kit Contents
5
Key Features
6
Spartan-6 FPGA
6
Configuration
6
Memory
6
Communications and Networking
6
Expansion Connectors
7
Clocking
7
Display
7
Control
7
Power
7
Getting Started with the Base Reference Design Demonstration
8
Setting up the SP605 Board for the BRD Demonstration
9
Installing the Application GUI
9
Default Jumper Settings
11
Connecting the Cables and Compactflash Memory Card
11
Setting the CF Configuration Mode
12
Starting the Base Reference Design GUI Application
13
Setting Ethernet Link
15
Selecting an Image
16
Changing the Filter
17
Getting Started with the Diagnostic Flash Demonstration
18
Setting the Default Jumper Settings
18
Installing Compactflash Card, USB UART Cable, and 12V Power
18
Setting the Mode Select and System ACE CF Select Switches
19
Installing the USB UART Cable and Driver
19
Setting up a Terminal Program
20
Configure with bist Diagnostic Design
21
Running the Diagnostic Demonstration
22
Installing the ISE Software
23
Redeeming the Software and IP License
23
Getting Additional Help and Support
28
Warranty
28
Appendix A: References
31
Support Resources
31
Spartan-6 FPGA Documents
31
Xilinx Spartan-6 FPGA Series User Manual (40 pages)
FPGA GTP Transceiver Signal Integrity Simulation Kit
Brand:
Xilinx
| Category:
Transceiver
| Size: 4 MB
Table of Contents
Revision History
2
Table of Contents
3
Preface: about this Guide
5
Guide Contents
5
Additional Support Resources
5
Typographical Conventions
5
Online Document
6
Chapter 1: Spartan-6 FPGA GTP Transceiver Signal Integrity Simulation Kit
7
Introduction
7
Release Notes for the GTP Transceiver SIS Kit
7
Installation and Requirements
7
SIS Kit Version 1.0
7
File Hierarchy
8
Getting Started
9
Opening an Example
9
Modifying the Driver Settings
10
Customizing the Channel Representation
12
Modifying the Receiver Settings
13
Adjusting Simulation Settings
14
Running the Simulation
16
Appendix A: Frequently Asked Questions
17
All Versions
17
Appendix B: HSPICE and Hyperlynx/Eldo Correlation Results
21
Introduction
21
GTP REFCLK Model Correlation
23
GTP Transceiver Model Correlation
27
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