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Xilinx Virtex-5 FPGA ML561 User Manual

Memory interfaces development board
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Virtex-5 FPGA ML561
Memory Interfaces
Development Board
User Guide
UG199 (v1.2.1) June 15, 2009
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Summary of Contents for Xilinx Virtex-5 FPGA ML561

  • Page 1 Virtex-5 FPGA ML561 Memory Interfaces Development Board User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 2: Revision History

    Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Table Of Contents

    ..............9 Chapter 1: Introduction About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit Virtex-5 FPGA ML561 Memory Interfaces Development Board...
  • Page 4 ..........91 www.xilinx.com ......93 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 5 Array Connector Numbering ..........139 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 6 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 7: Preface: About This Guide

    About This Guide This user guide describes the Virtex Board. Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on the Xilinx website at http://www.xilinx.com/virtex5. Guide Contents This manual contains the following chapters: Chapter 1, “Introduction” Chapter 2, “Getting Started”...

  • Page 8: Additional Support Resources

    PCB and interface level. Additional Support Resources To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support. ®...

  • Page 9: Conventions

    Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Meaning or Use...
  • Page 10 Low as long as the signal remains below this voltage. (This parameter is basically the hysteresis for logic ‘0’.) VIH(max) must not exceed 1.9V for all Micron Parts. www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 11: Chapter 1: Introduction

    For assistance with any of these items, contact your local Xilinx distributor or visit the Xilinx online store at www.xilinx.com. The heart of the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit is the Virtex-5 FPGA ML561 Development Board. This manual provides comprehensive information on Rev A3 and later revisions of this board.

  • Page 12: Virtex-5 Fpga Ml561 Memory Interfaces Development Board

    Chapter 1: Introduction Virtex-5 FPGA ML561 Memory Interfaces Development Board A high-level functional block diagram of the Virtex-5 FPGA ML561 Memory Interfaces Development Board is shown in External Interfaces: System ACE Controller, USB, RS-232, LCD SSTL18/SSTL2 FPGA #1 XC5VLX50T/ FFG1136...
  • Page 13 A i l N Figure 1-2: Virtex-5 FPGA ML561 Development Board Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Virtex-5 FPGA ML561 Memory Interfaces Development Board shows the Virtex-5 FPGA ML561 Development Board and indicates the 10 t www.xilinx.com 32-bit DDR400...
  • Page 14 Chapter 1: Introduction www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 15: Chapter 2: Getting Started

    “Applying Power to the Board” Documentation and Reference Design CD The CD included in the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit contains the design files for the Virtex-5 FPGA ML561 Development Board, including schematics, board layout, and reference design files. Open the ReadMe.rtf file on the CD to review the list of contents.

  • Page 16: Applying Power To The Board

    ML561 Development Board. To select the startup file, check that SW8 is set to position Applying Power to the Board The Virtex-5 FPGA ML561 Development Board is now ready to power on. The Virtex-5 FPGA ML561 Development Board is shipped with a country-specific AC line cord for the universal input 5V desktop power supply.

  • Page 17: Chapter 3: Hardware Description

    Hardware Description This chapter describes the major hardware blocks on the Virtex-5 FPGA ML561 Development Board and provides useful design consideration. It contains the following sections: “Hardware Overview” “Memory Details” “External Interfaces” “Power Regulation” “Board Design Considerations” Hardware Overview The ML561 Development/Evaluation system reference design is implemented with three XC5VLX50T-FFG1136 devices from the Virtex-5 FPGA family to demonstrate high-speed external memory application interfaces.

  • Page 18: Fpga

    35 mm x 35 mm BGA package. with the three FPGAs. Refer to Virtex-5 devices on the board. Refer to components on the Virtex-5 FPGA ML561 Development Board, including their reference designators and links to their corresponding data sheets. SSTL18 SSTL2 &...

  • Page 19: Memories

    9:1 data/strobe ratio for the QDRII device. DDR400 SDRAM Components The Virtex-5 FPGA ML561 Development Board has two 200 MHz Micron MT46V32M16BN-5B (16-bit) DDR400 SDRAM components that provide a 32-bit interface. Each 16-bit device is packaged in a 60-ball FBGA package, with a common address and control bus and separate clocks and DQS/DQ signals.

  • Page 20: Ddr2 Sdram Components

    BY0-BY7, CB0_7 DQ and DQS BY8-BY15, CB8_15 Address and Commands DIMM1 Control DIMM2 Control DIMM3 Control DIMM4 Control DIMM5 Control Figure 3-2: DDR2 Deep and Wide DIMM Sockets www.xilinx.com UG199_c3_02_050106 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 21: Memory Details

    Memory Details DDR400 and DDR2 Component Memories The FPGA #1 device on the Virtex-5 FPGA ML561 Development Board is connected to DDR and DDR2 component memories, as shown in Figure 3-3 signals among the different banks of the FPGA #1 device.
  • Page 22 DDR2 Component Differential Clock DDR2 Component Control Signals DDR2 Data and Strobe: Byte 0 DDR2 Data and Strobe: Byte 1 DDR2 Data and Strobe: Byte 2 DDR2 Data and Strobe: Byte 3 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 23: Ddr2 Sdram Dimm

    DDR2 SDRAM DIMM The FPGA #2 device on the Virtex-5 FPGA ML561 Development Board is connected to DDR2 memories. The DDR2 memory interface includes a 144-bit wide DIMM connection to up to five 240-pin DDR2 DIMM sockets. For the 144-bit wide DIMM datapath, the data bytes are spread across multiple banks of the FPGA #2 device.
  • Page 24 DDR2 DIMM Data, Strobes, and Data Mask: Check Byte 0 DDR2 DIMM Data, Strobes, and Data Mask: Check Byte 1 Serial PROM Address Serial PROM interface CLK and Data www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 25: Qdrii And Rldram Ii Memories

    BANK 122 BANK 126 Figure 3-5: FPGA #3 Banks for QDRII SRAM and RLDRAM II Interfaces (Top View) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 summarizes the distribution of QDRII and RLDRAM II component interface BANK 20 (40) RLDII Data DQ 0, 1 &...
  • Page 26 RLDRAM II Differential Clock RLDRAM II Differential Clock RLDRAM II Control Signals RLDRAM II Data and Strobes: Bytes 1:0 RLDRAM II Data and Strobes: Bytes 3:2 www.xilinx.com Virtex-5 FPGA ML561 User Guide Appendix A, “FPGA Description UG199 (v1.2.1) June 15, 2009...

  • Page 27: External Interfaces

    External Interfaces The external interfaces of the Virtex-5 FPGA ML561 Development Board are described in this section. RS-232 The ML561 board provides an RS-232 serial interface using a Maxim MAX3316ECUP device. The maximum speed of this device is 460 Kbps.

  • Page 28: 200 Mhz Lvpecl Clock

    The application using this clock source as an input to the PLL on the Virtex-5 device has not yet been fully verified. Signal Name DIRECT_CLK_TO_FPGA1_P DIRECT_CLK_TO_FPGA1_N DIRECT_CLK_TO_FPGA2_P DIRECT_CLK_TO_FPGA2_N DIRECT_CLK_TO_FPGA3_P DIRECT_CLK_TO_FPGA3_N Signal Name EXT_CLK_TO_FPGA1_P EXT_CLK_TO_FPGA1_N EXT_CLK_TO_FPGA2_P EXT_CLK_TO_FPGA2_N EXT_CLK_TO_FPGA3_P EXT_CLK_TO_FPGA3_N www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 29: 33 Mhz System Ace Controller Oscillator

    One four-position DIP switch per FPGA (for a total of three) is available to externally pull up or pull down a signal on the FPGA. This can be used to manually set values used by the design running on the FPGA. Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Name...

  • Page 30: Seven-Segment Displays

    Light Emitting Diodes (LEDs) Each FPGA is able to control four active-high green LEDs. The green is used to distinguish the User LEDs from the blue system LEDs on the Virtex-5 FPGA ML561 Development Board. Pushbuttons The ML561 board contains two momentary pushbuttons.

  • Page 31: Power On Or Off Slide Switch

    The power can be computed by measuring the voltage drop across each of these resistors. +5V or +12V Figure 3-7: Virtex-5 FPGA ML561 Development Board Power Measurement System Table 3-15: Power Measurement Header Pins (P102) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 32: Liquid Crystal Display Connector

    (P104). The LCD panel needs to hang off the edge of the board as shown in Header Signal Power Header Pin # VCC1V8_SENSE+ VCC1V8_SENSE- VCC1V8_MON VCC1V5_SENSE+ VCC1V5_SENSE- VCC1V5_MON VCC2V6_SENSE+ VCC2V6_SENSE- VCC2V6_MON VCC5_SENSE+ VCC5_SENSE- VCC5_MON VCC5 www.xilinx.com Figure 3-8. Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 33: Power Regulation

    The product specification at http://www.displaytech.com.hk/pdf/graphic/64128e%20series-v10.PDF information. Power Regulation This section describes the devices that supply power to the Virtex-5 FPGA ML561 Development Board. For electrical requirements and power consumption, see “Electrical Requirements.” Power Distribution The ML561 board uses +5V to drive numerous voltage regulators.

  • Page 34: Voltage Regulators

    J25 (RED) for +5V and J24 (BLACK) for GND. The Rev-A assembly of the Virtex-5 FPGA ML561 Development Board does not support the +12V input via jack J23 or via banana jacks J18 (RED) for +12V and J17 (BLACK) for GND.
  • Page 35 The TI PTH05010-WAZ and TI PTH05000-ADJ regulator outputs can be enabled or inhibited through the use of on-board two-pin jumpers. The inhibit jumpers use the following conventions: Jumper OFF = Enabled Jumper ON = Inhibited Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 VMARGIN_DN_N High High...

  • Page 36: Board Design Considerations

    Reduced thickness of the board (74 mils vs. 98 mils) resulting in reduced via inductance External terminations at both the memory and FPGA are provided for data signals for most of the memory interfaces on the Virtex-5 FPGA ML561 Development Board layout. The external V level. See Chapter 5, “Signal Integrity Recommendations,”...
  • Page 37 ML561 Revision A PCB. Refer to UG203, Virtex-5 PCB Designer’s Guide for more information on the PCB design using Virtex-5 devices. 73.90 ±7 mils Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Figure 3-11 1.0 oz, TOP, Z 3.8 mils, Er = 4.4...
  • Page 38 Split Power Plane #3 Ground Plane #3 50 ±5 Stripline Signal - Inner #3 Split Power Plane #4 50 ±5 Stripline Signal - Inner #4 Ground Plane #4 50 ±5 Microstrip Signal Bottom Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 39: Chapter 4: Electrical Requirements

    40W capacity of the 5V power brick. So an alternate 12V power input jack (J23) is provided on the Virtex-5 FPGA ML561 Development Board to hook up a 12V power brick, for example, CUI DTS120500U with a 60W capacity. The 12V is converted to 5V using the TI PTH12010WAS power module (VR11), which can supply up to 12A of current at 5V, or a 60W capacity.
  • Page 40 Micron RLDRAM II Data Sheet All signals. 500 mV swing around V ICS8304 Data Sheet ICS853006 Data Sheet DS080, System ACE CompactFlash Solution Epson EG2121CA Data Sheet Epson SG-8002CA Data Sheet Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 41 2.5V Power Plane 3.3V Power Plane 12V-to-5V Converter Notes: 1. [S] = 1.8V power for SSTL18 plane. 2. [H] = 1.8V power for HSTL18 plane. Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Current Power Quantity Voltage (V) (mA) 1.00...
  • Page 42 Chapter 4: Electrical Requirements Table 4-2 lists the 12 different power planes on the Virtex-5 FPGA ML561 Development Board. For the SSTL2, SSTL18, and HSTL power, separate power modules are implemented for V measurement for the FPGAs. The power modules for V TI PTH05010 modules, which have provisions for 5% voltage margining pins.
  • Page 43 Termination HSTL _VREF Power Plane (0.9V) XC5VLX50T-FFG1136: FPGA #1 (DDR2) XC5VLX50T-FFG1136: FPGA #2 (DDR2 DIMM) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 power planes. The positive values in the Excess Power column of Excess Voltage Current Power...
  • Page 44 TI PTH05010 15A Module Data 36.5 Sheet Micron DDR Component Data Sheet TI PTH05010 15A Module Data 14.5 Sheet All signals. 608 mV swing around V Fairchild FN6555 Data Sheet ICS8304 Data Sheet Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 45 3.3V Power Plane Capacity Total Power Consumed 12V-to-5V Power Module Capacity Notes: 1. [S] = 1.8V power for SSTL18 plane. 2. [H] = 1.8V power for HSTL18 plane. Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Excess Voltage Current Power...

  • Page 46: Fpga Internal Power Budget

    FPGA Internal Power Budget Table 4-4 summarizes power consumption estimates by each of the three XC5VLX50T-FFG1136 FPGAs on the Virtex-5 FPGA ML561 Development Board. This estimate derives the FPGA utilization information from the respective map report of a fully configured reference design.

  • Page 47: Chapter 5: Signal Integrity Recommendations

    The termination is placed at the end of the trace after the last load. Table 5-1 through Virtex-5 FPGA ML561 Development Board for the following five different memory interfaces. For each signal category, these tables include reference to the preliminary IBIS simulation results DDR400 SDRAM Components...
  • Page 48 No termination (use 75 ODT) No termination (use 75 ODT) 100 differential termination between pair 50 pull-up to 0.9V after the last component 50 pull-up to 0.9V after the last component Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 49 HSTL_I_DCI_18 (for SIO) Clock (CK, CK) DIFF_HSTL_I_18 Address (A, BA) Control (RAS, CAS, WE, CS, and CKE) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Termination and Transmission Line Summaries Termination at FPGA No termination No termination No termination...
  • Page 50 Chapter 5: Signal Integrity Recommendations www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 51: Configuration Modes

    Configuration This chapter provides a brief description of the FPGA configuration methods used on the Virtex-5 FPGA ML561 Development Board. This chapter contains the following sections: “Configuration Modes” “JTAG Chain” “JTAG Port” “Parallel IV Cable Port” “System ACE Interface” Configuration Modes The Virtex-5 FPGA ML561 Memory Interfaces Development Board includes several options to configure the Virtex-5 FPGAs.

  • Page 52: Jtag Chain

    Four devices (the System ACE chip and three XC5VLX50T-FFG1136 FPGAs) are connected via a JTAG chain on the Virtex-5 FPGA ML561 Development Board. The order of the four devices in the JTAG chain is System ACE chip (U45), FPGA #1 (U7), FPGA #2 (U5), and FPGA #3 (U34).
  • Page 53 Table 6-2 shows the System ACE interface signal names, descriptions, and pin assignments. Table 6-2: System ACE Interface Signal Descriptions System ACE Pin Number Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 SYSACE_MPA0 SYSACE_MPA1 SYSACE_MPA2 SYSACE_MPA3 SYSACE_MPA4 SYSACE_MPA5...
  • Page 54 Chapter 6: Configuration www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 55: Chapter 7: Ml561 Hardware-Simulation Correlation

    I/O buffer of the receiver device for the two significant corner driver conditions: slow- weak and fast-strong. The Virtex-5 FPGA ML561 Development Board implements five different memory interfaces: 32-bit DDR2 component...

  • Page 56: Test Setup

    Simulation software Mentor Graphics HyperLynx EXT, Version 7.5 with LineSim and BoardSim features Xilinx Virtex-5 FPGA IBIS package file: ff1136_5vlx50t.pkg, Rev 1.0 dated June 12, 2006 ML561, Rev B layout file: ML561_B_041706.hyp Micron DDR2-667 IBIS model for output and ODT input...
  • Page 57 9, does not change the eye pattern, as proven by sample simulation of one test signal with PRBS6, PRBS7, and PRBS9 stimuli. Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 (PRBS of order 6) test pattern stimulus is used for this analysis. The value of...

  • Page 58: Signal Integrity Correlation Results

    VIL(dc)-max = VREF – 100 mV = 0.8V for some definitions and routing terminologies. Table 3-19 in the www.xilinx.com VOH(ac) VIH(ac) VIL(ac) VOL(ac) UG199_c7_02_062707 of this signal “Board Design Considerations” section lists Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 59: Ddr2 Component Write Operation

    (84%) Extrapolation at IOB 1.39 ns fast-strong corner (92%) Notes: 1. DVW = Data Valid Window, ISI = Inter-Symbol Interference Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 49.1 ohms 49.1 ohms 58.3 ohms 47.132 ps 445.560 ps 25.244 ps...
  • Page 60 FPGA1 is controlled by DIP switches (SW2) as indicated in Table 7-3: DIP[1:2] Settings 2’b00 or 2’b11 2’b01 2’b10 Setting Normal alternating Write/Read sequence Write only, Refresh disabled Write once, then Read only, Refresh disabled www.xilinx.com Table 7-3. Description Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 61 Delta Voltage = 77.5 mV, Delta Time = 1.2222 ns (81.5% UI) Figure 7-5: DDR2 Component Write Correlation - Eye Scope Shot at Probe Point (Slow Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Probe 3:C9.1 (at pin) 0.000...
  • Page 62 Figure 7-7: DDR2 Component Write Correlation - Waveform Scope Shot at Probe Point (Slow Corner) (DDR2 Memory Via) Probe 3:C9.1 (at pin) 75.000 85.000 95.000 Time (ns) www.xilinx.com UG199_c7_06_071107 105.000 UG199_c7_07_070907 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 63 800.0 600.0 400.0 200.0 0.000 -200.0 Figure 7-9: DDR2 Component Write Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Probe 1:U12.D3 (at die) 200.0 600.0 1000.0 Time (ps) Probe 1:U12.D3 (at die)
  • Page 64 Figure 7-11: DDR2 Component Write Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner) Probe 1:U12.D3 (at die) 1200.0 1600.0 2000.0 Time (ps) Probe 1:U12.D3 (at die) 65.000 75.000 85.000 95.000 Time (ns) www.xilinx.com 2400.0 2800.0 UG199_c7_10_071007 105.000 UG199_c7_11_071007 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 65: Ddr2 Component Read Operation

    Refresh operation, the testbench on FPGA1 is controlled by the following DIP switch (SW2) setting: DIP[1:2] = 2’b10 – Write once, then Read only, Refresh disabled Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 49.1 ohms 49.1 ohms...
  • Page 66 Delta Voltage = 77.5 mV, Delta Time = 1.2846 ns (85.9% UI) Figure 7-14: DDR2 Component Read Correlation - Eye Scope Shot at Probe Point (Slow Corner) Probe 3:C7.1 (at pin) 1200.0 1600.0 2000.0 2400.0 Time (ns) UG199_c7_14_071107 www.xilinx.com UG199_c7_13_071107 2800.0 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 67 500.0 300.0 100.0 -100.0 65.000 Figure 7-16: DDR2 Component Read Correlation - Waveform Scope Shot at Probe Point (Slow Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Integrity Correlation Results Via) Probe 3:C7.1 (at pin) 75.000 85.000...
  • Page 68 Figure 7-18: DDR2 Component Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner) Probe 1:U7.P25 (at die) 1200.0 1600.0 2000.0 2400.0 Time (ps) UG199_c7_17_071007 Probe 1:U7.P25 (at die) 75.000 85.000 95.000 Time (ns) www.xilinx.com 2800.0 105.000 UG199_c7_18_071007 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 69 900.0 700.0 500.0 300.0 100.0 -100.0 Figure 7-20: DDR2 Component Read Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Probe 1:U7.P25 (at die) 1200.0 1600.0 2000.0 Time (ps) 65.000...

  • Page 70: Ddr2 Dimm Write Operation

    AutoPadstk_3_B00 DDR2_DIMM_DQ_... TL19 TL20 Virtex-5 FPGA DDR2_DQ_BY2_B3 DDR2_DI... DDR2_DI... DDR2_DI... 22.9 fF 96.3 fF 500.0 fF 46.4 fF UG199_c7_21_071907 Description Table 3-2, page 19 Figure 7-21 have added stubs for Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 71 FPGA2 is controlled by DIP switches (SW1) as indicated in Table 7-8: DIP[1:2] Settings 2’b00 or 2’b11 2’b01 2’b10 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Noise Margin (VIH + VIL) = Total (% UI) (% of VREF)
  • Page 72 Figure 7-23: DDR2 DIMM Write Correlation - Eye Scope Shot at Probe Point #1 (Slow Corner) Probe 3:C13.1 (at pin) 1200.0 1600.0 2000.0 2400.0 Time (ps) www.xilinx.com UG199_c7_22_071107 2800.0 UG199_c7_23_070907 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 73 200.0 0.000 -200.0 95.000 Figure 7-25: DDR2 DIMM Write Correlation - Waveform Scope Shot at Probe Point #1 (Slow Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Integrity Correlation Results Via) Probe 3:C13.1 (at pin) 105.000 115.000...
  • Page 74 Figure 7-27: DDR2 DIMM Write Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner) Probe 6:U3_B01.J1 (at die) 1000.0 1400.0 1800.0 2200.0 Time (ps) Probe 6:U3_B01.J1 (at die) 105.000 115.000 125.000 Time (ns) www.xilinx.com 2600.0 UG199_c7_26_071007 135.000 145.000 UG199_c7_27_071007 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 75 800.0 600.0 400.0 200.0 0.000 95.000 Figure 7-29: DDR2 DIMM Write Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Probe 6:U3_B01.J1 (at die) 800.0 1200.0 1600.0 2000.0 Time (ps) UG199_c7_28_071007 Probe 6:U3_B01.J1 (at die)

  • Page 76: Ddr2 Dimm Read Operation

    (623 + 613) = 1236 mV (137.3%) (524 + 504) = 1028 mV (114.2%) 208 mV (23.1%) (594 + 544) = 1138 mV (116.5%) (+481 + 508) = 989 mV (109.9%) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 77 Delta Voltage = 73.4 mV, Delta Time = 865.2 ps (59% UI) Figure 7-32: DDR2 DIMM Read Correlation - Eye Scope Shot at Probe Point (Slow Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Probe 3:C8.1 (at pin) 2000.0...
  • Page 78 25.000 Figure 7-34: DDR2 DIMM Read Correlation - Waveform Scope Shot at Probe Point (Slow Corner) Probe 3:C8.1 (at pin) 35.000 45.000 55.000 65.000 Time (ns) www.xilinx.com UG199_c7_33_071107 75.000 UG199_c7_34_071007 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 79 800.0 600.0 400.0 200.0 0.000 -200.0 Figure 7-36: DDR2 DIMM Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Probe 6:U5_B00.H29 (at die) 2400.0 2800.0 3200.0 Time (ps) Probe 6:U5_B00.H29 (at die)
  • Page 80 Figure 7-38: DDR2 DIMM Read Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner) Probe 6:U5_B00.H29 (at die) 800.0 1200.0 1600.0 Time (ps) Probe 6:U5_B00.H29 (at die) 30.000 40.000 50.000 60.000 Time (ns) www.xilinx.com 2000.0 2400.0 UG199_c7_37_071007 70.000 UG199_c7_38_071007 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 81: Qdrii Write Operation

    1.38 ns Extrapolation at IOB slow-weak corner (83%) 1.49 ns Extrapolation at IOB fast-strong corner (89%) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 49.0 ohms 49.8 ohms 45.1 ohms 11.902 ps 520.665 ps 7.862 ps 0.079 in 3.333 in...
  • Page 82 Delta Voltage = 101.9 mV, Delta Time = 1.3870 ns (83.5% UI) Figure 7-41: QDRII Write Correlation - Eye Scope Shot at Probe Point (Slow Corner) Probe 3:C7.1 (at pin) 0.000 400.0 800.0 1200.0 Time (ps) www.xilinx.com UG199_c7_40_071107 1600.0 UG199_c7_41_070907 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 83 700.0 500.0 300.0 100.0 -100.0 110.000 Figure 7-43: QDRII Write Correlation - Waveform Scope Shot at Probe Point (Slow Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Probe 3:C7.1 (at pin) 120.000 130.000 140.000 150.000 Time (ns) www.xilinx.com...
  • Page 84 Figure 7-45: QDRII Write Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner) Probe 6:U35.G11 (at die) 0.000 400.0 800.0 1200.0 Time (ps) Probe 6:U35.G11 (at die) 120.000 130.000 140.000 Time (ns) www.xilinx.com 1600.0 UG199_c7_44_070907 150.000 160.000 UG199_c7_45_071007 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 85 -100.0 -600.0 -1100.0 -1600.0 110.000 Figure 7-47: QDRII Write Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Integrity Correlation Results Probe 6:U35.G11 (at die) 1200.0 1600.0 2000.0 2400.0...

  • Page 86: Qdrii Read Operation

    (500 + 500) = 1000 mV (111.1%) (532 + 518) = 1050 mV (105.5%) 50 mV (5.6%) (608 + 575) = 1183 mV (131.5%) (532 + 661) = 1193 mV (132.6%) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 U35.F11...
  • Page 87 Delta Voltage = 97.9 mV, Delta Time = 983.8 ps (59% UI) Figure 7-50: QDRII Read Correlation - Eye Diagram Scope Shot at Probe Point (Slow Corner) Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Probe 3:C7.1 (at pin) 800.0...
  • Page 88 -100.0 20.000 Figure 7-52: QDRII Read Correlation - Waveform Scope Shot at Probe Point (Slow Corner) Probe 3:C7.1 (at pin) 30.000 40.000 50.000 60.000 Time (ns) www.xilinx.com UG199_c7_51_071107 70.000 UG199_c7_52_071007 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 89 900.0 700.0 500.0 300.0 100.0 -100.0 Figure 7-54: QDRII Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Probe 6:U34.G33 (at die) 1000.0 1400.0 1800.0 2200.0 Time (ps) Probe 6:U34.G33 (at die)
  • Page 90 Figure 7-56: QDRII Read Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner) Probe 6:U34.G33 (at die) 1200.0 1600.0 2000.0 2400.0 Time (ps) Probe 6:U34.G33 (at die) 35.000 45.000 55.000 Time (ns) www.xilinx.com 2800.0 UG199_c7_55_070907 65.000 75.000 UG199_c7_56_071007 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 91: Summary And Recommendations

    The values chosen between these two corner cases are: Minimum of DVW, noise margin, and overshoot/undershoot margin Maximum of ISI Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 contains this information for all six test signals. (% UI...
  • Page 92 253 mV 981 mV (28.1%) (109.0%) 546 mV 989 mV (60.7%) (109.9%) 687 mV 186 mV (76.3%) (20.7%) 509 mV 1183 mV (56.5%) (131.5%) 49, the recommendations remain the same Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 93: How To Generate A User-Specific Fpga Ibis Model

    Check ( ) the .ibs file again. There should not be any errors. Again, warnings are okay. 10. The result is an accurate custom-made IBIS model of a Virtex-5 device specific to your design. Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 How to Generate a User-Specific FPGA IBIS Model www.xilinx.com...
  • Page 94 Chapter 7: ML561 Hardware-Simulation Correlation www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 95: Appendix A: Fpga Pinouts

    FPGA Pinouts This appendix provides the pinouts for the three FPGAs on the Virtex-5 FPGA ML561 Development Board. The toolkit CD shipped with every ML561 contains sample UCFs for each memory interface. These UCFs are for pinout reference only and do not include other constraints, like I/O standards.
  • Page 96 DDR1_DQ_BY3_B3 DDR1_DQ_BY3_B4 DDR1_DQ_BY3_B5 DDR1_DQ_BY3_B6 DDR1_DQ_BY3_B7 DDR1_DQS_BY0_P DDR1_DQS_BY1_P DDR1_DQS_BY2_P DDR1_DQS_BY3_P DDR2 Component Interface DDR2_CAS_N DDR2_CK0_N DDR2_CK0_P DDR2_CK1_N DDR2_CK1_P DDR2_CKE DDR2_CS0_N DDR2_CS1_N DDR2_LB_BK15 DDR2_LB_BK15 DDR2_LB_BK19 DDR2_LB_BK19 DDR2_ODT0 DDR2_ODT1 DDR2_RAS_N www.xilinx.com AD32 AF33 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 97 DDR2_DQ_BY1_B2 DDR2_DQ_BY1_B3 DDR2_DQ_BY1_B4 DDR2_DQ_BY1_B5 DDR2_DQ_BY1_B6 DDR2_DQ_BY1_B7 DDR2_DQ_BY2_B0 DDR2_DQ_BY2_B1 23 CLK_TO_FPGA1_MGT_116_N CLK_TO_FPGA1_MGT_116_P CLK_TO_FPGA1_MGT_118_N CLK_TO_FPGA1_MGT_118_P DIRECT_CLK_TO_FPGA1_N Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Name DDR2 Component Interface (cont.) DDR2_DQ_BY2_B2 DDR2_DQ_BY2_B3 DDR2_DQ_BY2_B4 DDR2_DQ_BY2_B5 DDR2_DQ_BY2_B6 DDR2_DQ_BY2_B7 DDR2_DQ_BY3_B0 DDR2_DQ_BY3_B1 DDR2_DQ_BY3_B2 DDR2_DQ_BY3_B3...
  • Page 98 AC22 FPGA1_TDO 15 AD22 FPGA #1 Test and Debug Signals AG18 FPGA1_TEST_HDR_BY0_B6 AG15 FPGA1_TEST_HDR_BY0_B7 AH15 FPGA1_TEST_HDR_BY1_B0 AG20 FPGA1_TEST_HDR_BY1_B1 AF26 FPGA1_TEST_HDR_BY1_B2 FPGA1_TEST_HDR_BY1_B3 FPGA1_TEST_HDR_BY1_B4 FPGA1_TEST_HDR_BY1_B5 FPGA1_TEST_HDR_BY1_B6 FPGA1_TEST_HDR_BY1_B7 www.xilinx.com AD15 AB15 AC15 AD14 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 99 FPGA1_LCD_DB5 FPGA1_LCD_DB6 FPGA1_LCD_DB7 FPGA1_USB_CTS_N FPGA1_USB_DSR_N FPGA1_USB_DTR_N FPGA1_USB_RST_N VMARGIN_DN_3V3_N VMARGIN_DN_HSTL_N VMARGIN_DN_SSTL18_N VMARGIN_DN_SSTL2_N VMARGIN_DN_VCC1V0_N VMARGIN_DN_VCC2V5_N Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Name FPGA #1 Test Display Signals AG17 FPGA1_7SEG_6_N AH18 FPGA1_7SEG_DP_N AE18 FPGA1_LED0 AF18 FPGA1_LED1 AG16 FPGA1_LED2...

  • Page 100: Fpga #2 Pinout

    DDR2_DIMM2_CK2_P AB31 DDR2_DIMM2_CKE0 DDR2_DIMM2_CKE1 DDR2_DIMM2_CS0_N DDR2_DIMM2_CS1_N AJ32 DDR2_DIMM2_ODT0 AK32 DDR2_DIMM2_ODT1 DDR2_DIMM3_CK0_N DDR2_DIMM3_CK0_P DDR2_DIMM3_CK1_N DDR2_DIMM3_CK1_P DDR2_DIMM3_CK2_N www.xilinx.com AF26 AF25 AG25 AF24 AJ26 AH27 AE24 AD24 AE26 AE27 AA24 AC27 AB27 AA26 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 101 DDR2_DIMM_DM_BY0 DDR2_DIMM_DM_BY1 DDR2_DIMM_DM_BY2 DDR2_DIMM_DM_BY3 DDR2_DIMM_DM_BY4 DDR2_DIMM_DM_BY5 DDR2_DIMM_DM_BY6 DDR2_DIMM_DM_BY7 DDR2_DIMM_DM_CB0_7 DDR2_DIMM_DQ_BY0_B0 DDR2_DIMM_DQ_BY0_B1 DDR2_DIMM_DQ_BY0_B2 DDR2_DIMM_DQ_BY0_B3 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Name DDR2 DIMM Deep Interface (cont.) AA25 DDR2_DIMM_DQ_BY0_B4 AE28 DDR2_DIMM_DQ_BY0_B5 AH28 DDR2_DIMM_DQ_BY0_B6 DDR2_DIMM_DQ_BY0_B7 DDR2_DIMM_DQ_BY1_B0 AB26 DDR2_DIMM_DQ_BY1_B1...
  • Page 102 DDR2_DIMM_DQS_BY7_L_N AC32 DDR2_DIMM_DQS_BY7_L_P AD34 DDR2_DIMM_DQS_CB0_7_L_N AC34 DDR2_DIMM_DQS_CB0_7_L_P DDR2 DIMM Wide Interface AM13 DDR2_DIMM5_CK2_N AN13 DDR2_DIMM5_CK2_P AA10 DDR2_DIMM5_CKE0 AB10 DDR2_DIMM5_CKE1 www.xilinx.com AE34 AF34 AE32 AD32 AJ34 AH34 AP14 AN14 AC10 AM11 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 103 DDR2_DIMM_DQ_BY10_B0 DDR2_DIMM_DQ_BY10_B1 DDR2_DIMM_DQ_BY10_B2 DDR2_DIMM_DQ_BY10_B3 DDR2_DIMM_DQ_BY10_B4 DDR2_DIMM_DQ_BY10_B5 DDR2_DIMM_DQ_BY10_B6 DDR2_DIMM_DQ_BY10_B7 DDR2_DIMM_DQ_BY11_B0 DDR2_DIMM_DQ_BY11_B1 DDR2_DIMM_DQ_BY11_B2 DDR2_DIMM_DQ_BY11_B3 DDR2_DIMM_DQ_BY11_B4 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Name DDR2 DIMM Wide Interface (cont.) DDR2_DIMM_DQ_BY11_B5 DDR2_DIMM_DQ_BY11_B6 DDR2_DIMM_DQ_BY11_B7 DDR2_DIMM_DQ_BY12_B0 DDR2_DIMM_DQ_BY12_B1 DDR2_DIMM_DQ_BY12_B2 DDR2_DIMM_DQ_BY12_B3 DDR2_DIMM_DQ_BY12_B4 DDR2_DIMM_DQ_BY12_B5 DDR2_DIMM_DQ_BY12_B6...
  • Page 104 DDR2_DIMM_DQS_BY15_L_N DDR2_DIMM_DQS_BY15_L_P DDR2_DIMM_DQS_BY8_L_N DDR2_DIMM_DQS_BY8_L_P DDR2_DIMM_DQS_BY9_L_N DDR2_DIMM_DQS_BY9_L_P DDR2_DIMM_DQS_CB8_15_L_N DDR2_DIMM_DQS_CB8_15_L_P DDR2 DIMM Miscellaneous Signals DDR2_DIMM3_CNTL_PAR DDR2_DIMM3_CNTL_PAR_ERR DDR2_DIMM3_NC_019 DDR2_DIMM3_NC_102 AD26 DDR2_DIMM4_CNTL_PAR AD25 DDR2_DIMM4_CNTL_PAR_ERR AK28 DDR2_DIMM4_NC_019 AK27 DDR2_DIMM4_NC_102 www.xilinx.com AA28 AG28 AK29 AJ29 AL10 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 105 CLK_TO_FPGA2_MGT_P DIRECT_CLK_TO_FPGA2_N DIRECT_CLK_TO_FPGA2_P FPGA1_TO_FPGA2_MII_TX_CLK FPGA1_TO_FPGA2_MII_TX_DATA0 FPGA1_TO_FPGA2_MII_TX_DATA1 FPGA1_TO_FPGA2_MII_TX_DATA2 FPGA_INIT FPGA_PROGB FPGA_TMS FPGA_VBATT FPGA2_CCLK FPGA2_CNFG_M0 FPGA2_CNFG_M1 FPGA2_CNFG_M2 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Name DDR2_DIMM2_SA2 AM12 DDR2_DIMM3_SA0 DDR2_DIMM3_SA1 AL11 DDR2_DIMM3_SA2 DDR2_DIMM4_SA0 DDR2_DIMM4_SA1 DDR2_DIMM4_SA2 DDR2_DIMM5_SA0 DDR2_DIMM5_SA1 DDR2_DIMM5_SA2 FPGA #2 Clock and Reset Signals...
  • Page 106 AF18 FPGA2_LED1 AG16 FPGA2_LED2 AH17 FPGA2_LED3 FPGA #2 External Interfaces FPGA2_120_RX1_P FPGA2_124_TX0_N FPGA2_124_TX0_P FPGA2_124_TX1_N FPGA2_124_TX1_P www.xilinx.com AE23 AE22 AG12 AF13 AG23 AF23 AE12 AE13 AF19 AG21 AD19 AE19 AE17 AF16 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 107 Table A-2: FPGA #2 Pinout (Continued) Signal Name FPGA2_TXN0_BK120 FPGA2_TXN1_BK120 FPGA2_TXP0_BK120 FPGA2_TXP1_BK120 FPGA2_RS232_CTS FPGA2_RS232_RTS FPGA2_RS232_RX FPGA2_RS232_TX Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Name FPGA #2 External Interfaces (cont.) FPGA2_USB_CTS_N FPGA2_USB_DSR_N FPGA2_USB_DTR_N FPGA2_USB_RST_N FPGA2_USB_RTS_N FPGA2_USB_RX FPGA2_USB_SUSPEND FPGA2_USB_TX www.xilinx.com...

  • Page 108: Fpga #3 Pinout

    AF24 QDR2_D_BY0_B0 AJ26 QDR2_D_BY0_B1 AJ29 QDR2_D_BY0_B2 AK29 QDR2_D_BY0_B3 AC28 QDR2_D_BY0_B4 www.xilinx.com AB26 AB25 AA24 AC27 AB27 AA26 AJ27 AK26 AF28 AE28 AH28 AG28 AA28 AB28 AH27 AK33 AK34 AC29 AD30 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 109 QDR2_D_BY2_B5 QDR2_D_BY2_B6 QDR2_D_BY2_B7 QDR2_D_BY2_B8 QDR2_D_BY3_B0 QDR2_D_BY3_B1 QDR2_D_BY3_B2 QDR2_D_BY3_B3 QDR2_D_BY3_B4 QDR2_D_BY3_B5 QDR2_D_BY3_B6 QDR2_D_BY3_B7 QDR2_D_BY3_B8 QDR2_D_BY4_B0 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Name QDRII Memory Interface (cont.) QDR2_D_BY4_B1 QDR2_D_BY4_B2 QDR2_D_BY4_B3 QDR2_D_BY4_B4 QDR2_D_BY4_B5 QDR2_D_BY4_B6 QDR2_D_BY4_B7 QDR2_D_BY4_B8 QDR2_D_BY5_B0 QDR2_D_BY5_B1...
  • Page 110 QDR2_Q_BY5_B7 QDR2_Q_BY5_B8 QDR2_Q_BY6_B0 QDR2_Q_BY6_B1 QDR2_Q_BY6_B2 QDR2_Q_BY6_B3 QDR2_Q_BY6_B4 QDR2_Q_BY6_B5 QDR2_Q_BY6_B6 www.xilinx.com AP32 AN32 AN33 AN34 AM32 AM33 AL33 AL34 AK32 AF34 AE33 AF33 AB33 AC33 AB32 AC32 AD34 AC34 AA34 AA33 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 111 RLD2_A3 RLD2_A4 RLD2_A5 RLD2_A6 RLD2_A7 RLD2_A8 RLD2_A9 RLD2_BA0 RLD2_BA1 RLD2_BA2 RLD2_CK_BY0_1_N RLD2_CK_BY0_1_P Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Name QDRII Memory Interface (cont.) QDR2_Q_BY7_B4 QDR2_Q_BY7_B5 AB31 QDR2_Q_BY7_B6 QDR2_Q_BY7_B7 QDR2_Q_BY7_B8 RLDRAM II Memory Interface AD10 RLD2_CK_BY2_3_N...
  • Page 112 RLD2_DQ_BY0_B2 RLD2_DQ_BY0_B3 RLD2_DQ_BY0_B4 RLD2_DQ_BY0_B5 RLD2_DQ_BY0_B6 RLD2_DQ_BY0_B7 RLD2_DQ_BY0_B8 RLD2_DQ_BY1_B0 RLD2_DQ_BY1_B1 RLD2_DQ_BY1_B2 RLD2_DQ_BY1_B3 RLD2_DQ_BY1_B4 RLD2_DQ_BY1_B5 RLD2_DQ_BY1_B6 RLD2_DQ_BY1_B7 RLD2_DQ_BY1_B8 RLD2_DQ_BY2_B0 RLD2_DQ_BY2_B1 RLD2_DQ_BY2_B2 RLD2_DQ_BY2_B3 RLD2_DQ_BY2_B4 RLD2_DQ_BY2_B5 RLD2_DQ_BY2_B6 RLD2_DQ_BY2_B7 RLD2_DQ_BY2_B8 RLD2_DQ_BY3_B0 RLD2_DQ_BY3_B1 RLD2_DQ_BY3_B2 RLD2_DQ_BY3_B3 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 113 FPGA3_CNFG_M1 FPGA3_CNFG_M2 FPGA3_DIP0 FPGA3_DIP1 FPGA3_DIP2 FPGA3_DIP3 FPGA3_SPYHOLE_BK12 FPGA3_SPYHOLE_BK13 FPGA3_TEST_HDR_BY0_B0 FPGA3_TEST_HDR_BY0_B1 FPGA3_TEST_HDR_BY0_B2 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Name RLDRAM II Memory Interface (cont.) RLD2_DQ_BY3_B7 RLD2_DQ_BY3_B8 FPGA #3 Clock and Reset Signals EXT_CLK_TO_FPGA3_N EXT_CLK_TO_FPGA3_P AH22 FPGA3_LOW_FREQ_CLK...
  • Page 114 FPGA3_USB_RST_N FPGA3_USB_RTS_N FPGA3_USB_RX FPGA3_USB_SUSPEND FPGA3_USB_TX FPGA #3 System ACE Control Signals SYSACE_MPA5 SYSACE_MPA6 SYSACE_MPD0 SYSACE_MPD1 SYSACE_MPD2 SYSACE_MPD3 SYSACE_MPD4 SYSACE_MPD5 SYSACE_MPD6 SYSACE_MPD7 www.xilinx.com AE26 AE27 AF19 AG21 AD19 AE19 AE17 AF16 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 115: Appendix B: Bill Of Materials

    This appendix lists the bill of materials (BOM) for many of the components used for the assembly of the Virtex-5 FPGA ML561 Development Board, Revision A. Wherever feasible and practical, the associated reference designators are also listed for each part. The component part number in the “Mfr.
  • Page 116 U16, U22 R63, R724, R764, R777, R874, R885, R954 U37, U38 U30, U44 U17, U18 D17, D23, D35 J18, J25 J17, J24 P20, P21, P93 F1, F2 J16, J19, J20, J21 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 117 DO3316 Inductor Ferrite Bead 0805 (assorted values) 0402 (assorted values) Resistor 0603 (assorted values) 0805 (assorted values) Transistor MOSFET Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Manufacturer Mfr. Part Number ITT_INDUSTRIES SDA04H1KD Panasonic EVQ11L07K Panasonic EVQ11L05K APEM...
  • Page 118 Appendix B: Bill of Materials www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 119: Appendix C: Lcd Interface

    Board. General The Virtex-5 FPGA ML561 Development Board has a full graphical LCD panel. This display was chosen because of its possible use in embedded systems. A character-type display also can be connected because the graphical LCD has the same interface as the character-type LCD panels.

  • Page 120: Hardware Schematic Diagram

    Resistor to Gnd Backlight ON/OFF Figure C-1: Display Schematic Diagram www.xilinx.com Specification = V0 - V = 3V, x4 boost, V0 = 11V, 3.3V 3.3V 68xx 68xx Default = 68xx UG199_C_01_050106 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 121: Peripheral Device Ks0713

    Peripheral Device KS0713 Figure C-2 Circuit Circuit Circuit KS0713 Samsung Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 is a block diagram of the Samsung KS0713. 33 Common 132 Segment Driver Driver Circuits Circuits Segment Controller Page Display Data RAM...
  • Page 122 64128EFCBC-XLP LCD panel. 74.00 69.00 56.00 128 x 64 DOTS Dimensions in mm www.xilinx.com Parallel or Serial Selection. Default is Parallel. S128 LCD Panel LED Backlight UG199_C_03_050106 8.00 Max UG199_C_04_050106 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 123: Controller - Operation

    ADC control, and LCD outputs (segments). Table C-2: LCD Panel DB3 DB2 DB1 DB0 Data Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Hardware Schematic Diagram Table C-2...
  • Page 124 Appendix C: LCD Interface Table C-2: LCD Panel (Continued) DB3 DB2 DB1 DB0 Data Page 2 Page 3 Page 4 Page 5 www.xilinx.com Virtex-5 FPGA ML561 User Guide Line Address UG199 (v1.2.1) June 15, 2009...

  • Page 125: Controller - Lcd Panel Connections

    Controller – LCD Panel Connections The controller die, KS0713, connects to the LCD glass panel and user connection pins via a small PCB. Other necessary pins have default connections on the PCB. Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 www.xilinx.com...

  • Page 126: Controller - Power Supply Circuits

    The LCD operating voltage, V0, is set with two resistors R when the resistors are external. INTRS is driven High when the resistors are internal. For the Virtex-5 FPGA ML561 Development Board, internal resistors are selected. The LCD operating voltage (V0) and the Electronic Volume Voltage (V...

  • Page 127: Operation Example Of The 64128Efcbc-3Lp

    Voltage converter input is between 2.4V Internal voltage divider resistors Temperature coefficient is set to -0.05%/ C Normal power mode is set Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Figure C-6 shows the initialization procedure required to set up the LCD...
  • Page 128 When SHL is set to 1, the common lines are scanned in opposite direction. Initial Value 0,0,0 (VC, VR, VF) 0,0 (S1, S0) 0 (First line) 0,0,0 (R2, R1, R0) 1,0,0,0,0,0 (SV5, SV4, SV3, SV2, SV1, SV0) www.xilinx.com Virtex-5 FPGA ML561 User Guide Table C-3. UG199 (v1.2.1) June 15, 2009...
  • Page 129 After the display is brought to operational mode, it is best to wait at least 1 ms to ensure the stabilization of power supply levels. After this time, all other necessary display initializations can be performed. Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 1/7: when the BIAS bit is 0...

  • Page 130: Instruction Set

    This is a two-byte instruction. The first instruction sets the reference voltage mode. The second instruction sets the reference voltage parameter. BUSY ONOFF RESETB www.xilinx.com Read Data Write Data Line address 0 Line address 1 Line address 62 Line address 63 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 131 This instruction changes the relationship between RAM column address and segment driver. ADC = 0, SEG1 --> SEG132 default mode ADC = 1, SEG132 --> SEG1 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 www.xilinx.com Hardware Schematic Diagram...
  • Page 132 RAM bit data = '1' RAM bit data = '0' Pixel ON Pixel OFF Duty Bias = 0 Bias = 1 ratio 1/65 www.xilinx.com Pixel OFF Pixel ON Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 BIAS...

  • Page 133: Read/Write Characteristics (6800 Mode)

    Access Time Output Disable Time System Cycle Time Enable Pulse Width CS1B WRITE DB0-DB7 READ Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Signal Symbol DB7 to DB0 Read/Write E_RD Figure C-7: Read/Write Timing Waveforms (6800 Mode) www.xilinx.com...

  • Page 134: Design Examples

    At first, the block RAM must be initialized with some data (instructions to the LCD) to make the LCD operate correctly. panel in full graphics mode. Figure C-8 illustrates a general block diagram of the LCD www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 135: Lcd Panel Used In Character Mode

    (controller). The Toplevel.vhd.txt file provides a detailed description of the LCD controller interface. Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 IorD = '1' Instruction IorD (bit 9)
  • Page 136 RAM character set. The block RAM (see organized as small arrays of eight bytes, which is easy for address calculation. Figure C-9: ASCII Character Representations www.xilinx.com UG199_C_09_050106 Figure C-10) is Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...
  • Page 137 Because each character uses eight byte locations, character 0 in the character set starts from memory location 348 decimal. For example, character X has byte value 58h or 01011000b. Shifting this value three positions gives the value 2C0h or 704d. Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Data[7:0] 2047...
  • Page 138 Stop both counters at TC. Send character position and line to the LCD. Load new value in counter A. Switch to character ROM. Enable counters. www.xilinx.com Data LUT-ROM Display Initialization State Machine UG199_C_11_050106 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

  • Page 139: Array Connector Numbering

    Array Connector Numbering Figure C-12 Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 shows the LCD connections for Bank 0. Bank 0 Connector J32 Figure C-12: LCD Connections (Bank 0) www.xilinx.com Hardware Schematic Diagram Connector Pin LCD_D0 LCD_D4...
  • Page 140 Appendix C: LCD Interface www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009...

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