Overview - Texas Instruments SimpleLink CC2620 Technical Reference Manual

Overview

The Cortex-M3 processor closely integrates a nested vector interrupt controller (NVIC) to deliver fast
execution of interrupt service routines (ISRs) thereby dramatically reducing interrupt latency. The
hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations
further reduces interrupt latency. Interrupt handlers do not require any assembler stubs, thus removing
code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when
switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep
modes, including deep-sleep mode, which enables the entire device to be rapidly powered down.
t
NVIC
Serial Wire JTAG Debug
Debug Port Access Port
2.3 Overview
2.3.1 System-level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA
low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit
manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data
handling.
2.3.2 Integrated Configurable Debug
The Cortex-M3 processor implements a complete hardware-debug solution through a Serial Wire or JTAG
Debug Port (SWJ-DP) module. SWJ-DP provides a high system visibility of the processor and memory
through a traditional JTAG port. See
Architecture Specification for details on SWJ-DP.
For system trace, the processor integrates an instrumentation trace macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a
serial wire viewer (SWV) can export a stream of software-generated messages, data trace, and profiling
information through one pin.
30
The Cortex-M3 Processor
Figure 2-1. CPU Block Diagram
CM3 Core
Interrupts t
tSleept
Instructions Data
tDebugt
Flash Patch
and
Watchpoint
Breakpoint
Chapter
Copyright © 2015, Texas Instruments Incorporated
Instrumentation
Data
Trace Macrocell
and Trace
Advance
Peripheral Bus
tI-code Bust
tD-code Bust
tSystem Bust
technology to provide high-speed,
®
5, JTAG Interface, and the ARM
SWCU117C – February 2015 – Revised September 2015
www.ti.com
Trace Data
Trace Clock
Trace Port
Interface
Unit
Serial Wire
Viewer (SWV)
CPU_TIPROP_TRACECLKMUX
Register
ROM
Table
®
Debug Interface V5
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