Texas Instruments SimpleLink CC2620 Technical Reference Manual page 223

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3.2.2.1 Level-sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as
edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the
interrupt signal. The interrupt sources in CC26xx and CC13xx are normally level. That is, they stay active
until the interrupt source is cleared in the peripheral. Typically this happens because the interrupt service
routine (ISR) accesses the peripheral, causing it to clear the interrupt request. To ensure the NVIC detects
the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (see
Section 3.2.2.2, Hardware and Software Control of Interrupts). For a level-sensitive interrupt, if the signal
is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the
processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted
until it no longer needs servicing.
3.2.2.2 Hardware and Software Control of Interrupts
The Cortex-M3 processor latches all interrupts. A peripheral interrupt becomes pending for one of the
following reasons:
• The NVIC detects that the interrupt signal is asserted and the interrupt is not active.
• The NVIC detects a rising edge on the interrupt signal.
• Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt Register (STIR) to make a software-generated interrupt pending (see the NVIC_ISPR0
SETPENDn register bit in
A pending interrupt remains pending until one of the following occurs:
• The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to
active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the
interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might
cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes
to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the
state of the interrupt changes to pending and active. In this case, when the processor returns from
the ISR the state of the interrupt changes to pending, which might cause the processor to
immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR,
when the processor returns from the ISR the state of the interrupt changes to inactive.
• Software writes to the corresponding interrupt clear-pending register bit:
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does
not change. Otherwise, the state of the interrupt changes to inactive.
– For a pulse interrupt, the state of the interrupt changes to inactive if the state was pending, or to
active if the state was active and pending.
3.2.3 SCB
The SCB provides system implementation information and system control, including configuration, control,
and reporting of the system exceptions.
SWCU117C – February 2015 – Revised September 2015
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Section 2.7.4.10 or the STIR INTID register field in
Copyright © 2015, Texas Instruments Incorporated
Functional Description
Section 2.7.4.60).
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Cortex-M3 Peripherals