Texas Instruments SimpleLink CC2620 Technical Reference Manual page 352

Interrupts and Events Registers
4.7.2.67 UDMACH9SSEL Register (Offset = 548h) [reset = 45h]
UDMACH9SSEL is shown in
Output Selection for DMA Channel 9 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as
GPT0:RIS.DMAARIS.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-7 RESERVED
6-0 EV
352
Interrupts and Events
Figure 4-76 and described in
Figure 4-76. UDMACH9SSEL Register
RESERVED
R-0h
Table 4-81. UDMACH9SSEL Register Field Descriptions
Type Reset
R 0h
R/W 45h
Copyright © 2015, Texas Instruments Incorporated
Table 4-81.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Read/write selection value
0h = Always inactive
45h = Not used tied to 0
4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV
4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV
4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV
50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV
51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV
52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV
53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV
54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV
79h = Always asserted
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8 7 6 5 4 3 2 1
EV
R/W-45h
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