Texas Instruments SimpleLink CC2620 Technical Reference Manual page 181

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2.7.4.38 DFSR Register (Offset = D30h) [reset = 0h]
DFSR is shown in
Debug Fault Status
This register is used to monitor external debug requests, vector catches, data watchpoint match, BKPT
instruction execution, halt requests. Multiple flags in the Debug Fault Status Register can be set when
multiple fault conditions occur. The register is read/write clear. This means that it can be read normally.
Writing a 1 to a bit clears that bit. Note that these bits are not set unless the event is caught. This means
that it causes a stop of some sort. If halting debug is enabled, these events stop the processor into debug.
If debug is disabled and the debug monitor is enabled, then this becomes a debug monitor handler call, if
priority permits. If debug and the monitor are both disabled, some of these events are Hard Faults, and
some are ignored.
31 30
23 22
15 14
7 6
RESERVED
R/W-0h
Bit Field
31-5 RESERVED
4 EXTERNAL
3 VCATCH
2 DWTTRAP
1 BKPT
0 HALTED
SWCU117C – February 2015 – Revised September 2015
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Figure 2-108 and described in
Figure 2-108. DFSR Register
29 28
21 20
13 12
5 4
EXTERNAL
R/W-0h
Table 2-134. DFSR Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-134.
27
RESERVED
R/W-0h
19
RESERVED
R/W-0h
11
RESERVED
R/W-0h
3
VCATCH DWTTRAP
R/W-0h R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
External debug request flag. The processor stops on next instruction
boundary.
0x0: External debug request signal not asserted
0x1: External debug request signal asserted
Vector catch flag. When this flag is set, a flag in one of the local fault
status registers is also set to indicate the type of fault.
0x0: No vector catch occurred
0x1: Vector catch occurred
Data Watchpoint and Trace (DWT) flag. The processor stops at the
current instruction or at the next instruction.
0x0: No DWT match
0x1: DWT match
BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch
code, and also by normal code. Return PC points to breakpoint
containing instruction.
0x0: No BKPT instruction execution
0x1: BKPT instruction execution
Halt request flag. The processor is halted on the next instruction.
0x0: No halt request
0x1: Halt requested by NVIC, including step
Cortex-M3 Processor Registers
26 25
18 17
10 9
2 1
BKPT
R/W-0h
24
16
8
0
HALTED
R/W-0h
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