Texas Instruments SimpleLink CC2620 Technical Reference Manual page 469

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6.2.3.11 RECHARGESTAT Register (Offset = 34h) [reset = 0h]
RECHARGESTAT is shown in
Recharge Controller Status
This register controls various status registers which are updated during recharge. The register is mostly
intended for test and debug.
31 30 29 28
15 14 13 12
Bit Field
31-20 RESERVED
19-16 VDDR_SMPLS
15-0 MAX_USED_PER
SWCU117C – February 2015 – Revised September 2015
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Figure 6-36 and described in
Figure 6-36. RECHARGESTAT Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
MAX_USED_PER
R/W-0h
Table 6-40. RECHARGESTAT Register Field Descriptions
Type Reset
R 0h
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-40.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
The last 4 VDDR samples, bit 0 being the newest.
The register is being updated in every recharge period with a shift
left, and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet
in in case VDDR > VDDR_threshold just before recharge starts.
Otherwise a 0 will be shifted in.
The maximum value of recharge period seen with VDDR>threshold.
The VDDR voltage is compared against the threshold voltage at just
before each recharge. If VDDR is above threshold,
MAX_USED_PER is updated with max ( current recharge peride
MAX_USED_PER ) This way MAX_USED_PER can track the
recharge period where VDDR is decharged to the threshold value.
We can therefore use the value as an indication of the leakage
current during recharge.
This bitfield is cleared to 0 when writing this register.
Power, Reset, and Clock Management
PRCM Registers
19 18 17 16
VDDR_SMPLS
R-0h
3 2 1 0
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