Texas Instruments SimpleLink CC2620 Technical Reference Manual page 159

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2.7.4.20 NVIC_IPR3 Register (Offset = 40Ch) [reset = 0h]
NVIC_IPR3 is shown in
Irq 12 to 15 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_15
R/W-0h
Bit Field
31-24 PRI_15
23-16 PRI_14
15-8 PRI_13
7-0 PRI_12
SWCU117C – February 2015 – Revised September 2015
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Figure 2-90 and described in
Figure 2-90. NVIC_IPR3 Register
PRI_14
R/W-0h
Table 2-116. NVIC_IPR3 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-116.
9
PRI_13
R/W-0h
Description
Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details).
Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details).
Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details).
Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details).
Cortex-M3 Processor Registers
8 7 6 5 4 3 2 1
PRI_12
R/W-0h
0
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