Texas Instruments SimpleLink CC2620 Technical Reference Manual page 136

Cortex-M3 Processor Registers
2.7.4.7 NVIC_ISER0 Register (Offset = 100h) [reset = 0h]
NVIC_ISER0 is shown in
Irq 0 to 31 Set Enable
This register is used to enable interrupts and determine which interrupts are currently enabled.
31 30
SETENA31 SETENA30
R/W-0h R/W-0h
23 22
SETENA23 SETENA22
R/W-0h R/W-0h
15 14
SETENA15 SETENA14
R/W-0h R/W-0h
7 6
SETENA7 SETENA6
R/W-0h R/W-0h
Bit Field
31 SETENA31
30 SETENA30
29 SETENA29
28 SETENA28
27 SETENA27
26 SETENA26
25 SETENA25
24 SETENA24
23 SETENA23
22 SETENA22
21 SETENA21
136
Figure 2-77 and described in
Figure 2-77. NVIC_ISER0 Register
29 28
SETENA29 SETENA28
R/W-0h R/W-0h
21 20
SETENA21 SETENA20
R/W-0h R/W-0h
13 12
SETENA13 SETENA12
R/W-0h R/W-0h
5 4
SETENA5 SETENA4
R/W-0h R/W-0h
Table 2-103. NVIC_ISER0 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-103.
27 26
SETENA27 SETENA26
R/W-0h R/W-0h
19 18
SETENA19 SETENA18
R/W-0h R/W-0h
11 10
SETENA11 SETENA10
R/W-0h R/W-0h
3 2
SETENA3 SETENA2
R/W-0h R/W-0h
Description
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details).
Reading the bit returns its current enable state.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
SETENA25 SETENA24
R/W-0h R/W-0h
17 16
SETENA17 SETENA16
R/W-0h R/W-0h
9 8
SETENA9 SETENA8
R/W-0h R/W-0h
1 0
SETENA1 SETENA0
R/W-0h R/W-0h
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