Exception States - Texas Instruments SimpleLink CC2620 Technical Reference Manual

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4.1 Exception Model
The ARM Cortex-M3 processor and the nested vectored interrupt controller (NVIC) prioritize and handle all
exceptions in handler mode. The state of the processor is automatically stored to the stack on an
exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The
vector is fetched in parallel to state saving, thus enabling efficient interrupt entry. The processor supports
tail-chaining, which enables performance of back-to-back interrupts without the overhead of state saving
and restoration.
Table 4-1 lists all exception types. Software can set eight priority levels on seven of these exceptions
(system handlers) as well as on CC26xx and CC13xx interrupts (listed in
Priorities on the system handlers are set with the NVIC System Handler Priority n Registers
(CPU_SCS:SHPRn). Interrupts are enabled through the NVIC Interrupt Set Enable n Register
(CPU_SCS:NVIC_ISERn) and prioritized with the NVIC Interrupt Priority n Registers
(CPU_SCS:NVIC_IPRn). Priorities can be grouped by splitting priority levels into preemption priorities and
subpriorities. All the interrupt registers are described in
Internally, the highest user programmable priority (0) is treated as third priority, after a reset, and a hard
fault, in that order.
NOTE: 0 is the default priority for all the programmable priorities.
After a write to clear an interrupt source, it may take several processor cycles
for the NVIC to detect the interrupt source deassertion. Thus, if the interrupt
clear is done as the last action in an interrupt handler, it is possible for the
interrupt handler to complete while the NVIC detects the interrupt as still
asserted, causing the interrupt handler to be re-entered errantly. This situation
can be avoided by either clearing the interrupt source at the beginning of the
interrupt handler or by performing a read or write after the write to clear the
interrupt source (and flush the write buffer).
For more information on exceptions and interrupts, see

4.1.1 Exception States

Each exception is in one of the following states:
• Inactive: The exception is not active and not pending.
• Pending: The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
• Active: An exception is being serviced by the processor but has not completed. An exception handler
can interrupt the execution of another exception handler. In this case, both exceptions are in the active
state.
• Active and Pending: The exception is being serviced by the processor, and there is a pending
exception from the same source.
4.1.2 Exception Types
The exception types are:
• Reset: Reset is invoked on power up or a warm reset. The exception model treats reset as a special
form of exception. When reset is asserted, the operation of the processor stops, potentially at any point
in an instruction. When reset is deasserted, execution restarts from the address provided by the reset
entry in the vector table. Execution restarts as privileged execution in thread mode.
• Hard Fault: A hard fault is an exception that occurs because of an error during exception processing,
or because an exception cannot be managed by any other exception mechanism. Hard faults have a
fixed priority of –1, meaning they have higher priority than any exception with configurable priority.
SWCU117C – February 2015 – Revised September 2015
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Section
CAUTION
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Copyright © 2015, Texas Instruments Incorporated
Table 4-8).
3.2.2, Cortex M3 Peripherals chapter.
3.2.2, Cortex M3 Peripherals chapter.
Interrupts and Events
Exception Model
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