Fault Handling - Texas Instruments SimpleLink CC2620 Technical Reference Manual

Fault Handling

EXC_RETURN[31:0]
0xFFFF FFF0
0xFFFF FFF1
0xFFFF FFF2 to 0xFFFF FFF8
0xFFFF FFF9
0xFFFF FFFA to 0xFFFF FFFC
0xFFFF FFFD
0xFFFF FFFE to 0xFFFF FFFF
4.2 Fault Handling
Faults are a subset of the exceptions (see
generate a fault:
• A bus error on an instruction fetch or vector table load or a data access
• An internally detected error such as an undefined instruction or an attempt to change state with a BX
instruction
4.2.1 Fault Types
Table 4-4 lists the types of fault, the handler used for the fault, the corresponding fault status register, and
the register bit that indicates the fault has occurred. For more information about the fault status registers,
see CPU_SCS:CFSR in
Fault
Bus error on a vector read
Fault escalated to a hard fault
Bus error during exception
stacking
Bus error during exception
unstacking
Bus error during instruction
prefetch
Precise data bus error
Imprecise data bus error
Attempt to access a
coprocessor
Undefined instruction
Attempt to enter an invalid
(1)
instruction set state
Invalid EXC_RETURN value
Illegal unaligned load or store
Divide by 0
(1)
Trying to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI
continuation.
236
Interrupts and Events
Table 4-3. Exception Return Behavior
Description
Reserved
Return to handler mode
Exception return uses state from MSP
Execution uses MSP after return.
Reserved
Return to thread mode: VTOR
Exception return uses state from MSP
Execution uses MSP after return.
Reserved
Return to thread mode
Exception return uses state from PSP
Execution uses PSP after return
Reserved
Section
Section 2.7.4.36, CFSR Register (Offset = D28h) [reset = X].
Table 4-4. Faults
Handler
Hard fault
Hard fault
Bus fault
Bus fault
Bus fault
Bus fault
Bus fault
Usage fault
Usage fault
Usage fault
Usage fault
Usage fault
Usage fault
Copyright © 2015, Texas Instruments Incorporated
4.1, Exception Model). The following conditions
Fault Status Register
Hard Fault Status (HFSR)
Hard Fault Status (HFSR)
Bus Fault Status (BFSR)
Bus Fault Status (BFSR)
Bus Fault Status (BFSR)
Bus Fault Status (BFSR)
Bus Fault Status (BFSR)
Usage Fault Status (UFSR)
Usage Fault Status (UFSR)
Usage Fault Status (UFSR)
Usage Fault Status (UFSR)
Usage Fault Status (UFSR)
Usage Fault Status (UFSR)
SWCU117C – February 2015 – Revised September 2015
www.ti.com
Bit Name
VECTTBL
FORCED
STKERR
UNSTEKRR
IBUSERR
PRECISERR
IMPRECISERR
NOCP
UNDEFINSTR
INVSTATE
INVPC
UNALIGNED
DIVBYZERO
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