Texas Instruments SimpleLink CC2620 Technical Reference Manual page 52

Cortex-M3 Processor Registers
2.7.1.1 CTRL Register (Offset = 0h) [reset = 40000000h]
CTRL is shown in
Control
Use the DWT Control Register to enable the DWT unit.
31 30
23 22
RESERVED CYCEVTENA
R/W-0h R/W-0h
15 14
RESERVED
R/W-0h
7 6
POSTCNT
R/W-0h
Bit Field
31-26 RESERVED
25 NOCYCCNT
24 NOPRFCNT
23 RESERVED
22 CYCEVTENA
21 FOLDEVTENA
20 LSUEVTENA
19 SLEEPEVTENA
18 EXCEVTENA
52
Figure 2-4 and described in
Figure 2-4. CTRL Register
29 28
RESERVED
R/W-10h
21 20
FOLDEVTENA LSUEVTENA
R/W-0h R/W-0h
13 12
PCSAMPLEEN
A
R/W-0h
5 4
Table 2-27. CTRL Register Field Descriptions
Type Reset
R/W 10h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-27.
27 26
19 18
SLEEPEVTEN EXCEVTENA
A
R/W-0h R/W-0h
11 10
SYNCTAP
R/W-0h
3 2
POSTPRESET
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
When set, CYCCNT is not supported.
When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and
CPICNT are not supported.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Enables Cycle count event. Emits an event when the POSTCNT
counter triggers it. See CYCTAP and POSTPRESET for details. This
event is only emitted if PCSAMPLEENA is disabled.
PCSAMPLEENA overrides the setting of this bit.
0: Cycle count events disabled
1: Cycle count events enabled
Enables Folded instruction count event. Emits an event when
FOLDCNT overflows (every 256 cycles of folded instructions). A
folded instruction is one that does not incur even one cycle to
execute. For example, an IT instruction is folded away and so does
not use up one cycle.
0: Folded instruction count events disabled.
1: Folded instruction count events enabled.
Enables LSU count event. Emits an event when LSUCNT overflows
(every 256 cycles of LSU operation). LSU counts include all LSU
costs after the initial cycle for the instruction.
0: LSU count events disabled.
1: LSU count events enabled.
Enables Sleep count event. Emits an event when SLEEPCNT
overflows (every 256 cycles that the processor is sleeping).
0: Sleep count events disabled.
1: Sleep count events enabled.
Enables Interrupt overhead event. Emits an event when EXCCNT
overflows (every 256 cycles of interrupt overhead).
0x0: Interrupt overhead event disabled.
0x1: Interrupt overhead event enabled.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
NOCYCCNT NOPRFCNT
R/W-0h R/W-0h
17 16
CPIEVTENA EXCTRCENA
R/W-0h R/W-0h
9 8
CYCTAP POSTCNT
R/W-0h R/W-0h
1 0
CYCCNTENA
R/W-0h
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