Texas Instruments SimpleLink CC2620 Technical Reference Manual page 506

PRCM Registers
6.2.4.31 GPTCLKDIV Register (Offset = CCh) [reset = 0h]
GPTCLKDIV is shown in
GPT Scalar
31 30 29 28
15 14 13 12
Bit Field
31-4 RESERVED
3-0 RATIO
506
Power, Reset, and Clock Management
Figure 6-70 and described in
Figure 6-70. GPTCLKDIV Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
RESERVED
R-0h
Table 6-75. GPTCLKDIV Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-75.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Scalar used for GPTs. The division rate will be constant and ungated
for Run / Sleep / DeepSleep mode.
For changes to take effect, CLKLOADCTL.LOAD needs to be written
Other values are not supported.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 4
3h = Divide by 8
4h = Divide by 16
5h = Divide by 32
6h = Divide by 64
7h = Divide by 128
8h = Divide by 256
SWCU117C – February 2015 – Revised September 2015
www.ti.com
19 18 17 16
3 2 1 0
RATIO
R/W-0h
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