Texas Instruments SimpleLink CC2620 Technical Reference Manual page 731

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9.2.1.12 CONFIG_SYNTH_DIV15 Register (Offset = ECh) [reset = FFFFFFFFh]
CONFIG_SYNTH_DIV15 is shown in
Configuration of Synthesizer in Divide-by-15 Mode
Divide-by-15 mode is only available for CC13xx.
31 30 29 28
RESERVED
R-Fh
15 14 13 12
RFC_MDM_DEMIQMC0
R-FFFFh
Bit Field
31-28 RESERVED
27-12 RFC_MDM_DEMIQMC0
11-6 LDOVCO_TRIM_OUTPU
T
5-0 SLDO_TRIM_OUTPUT
SWCU117C – February 2015 – Revised September 2015
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Figure 9-34
Figure 9-34. CONFIG_SYNTH_DIV15 Register
27 26 25
11 10 9
LDOVCO_TRIM_OUTPUT
R-3Fh
Table 9-36. CONFIG_SYNTH_DIV15 Register Field Descriptions
Type Reset
R Fh
R FFFFh
R 3Fh
R 3Fh
Copyright © 2015, Texas Instruments Incorporated
and described in Table
24 23 22 21
RFC_MDM_DEMIQMC0
R-FFFFh
8 7 6 5
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and
RFC_MDM:DEMIQMC0.PHASEFACTOR
Value is read by RF Core ROM FW during RF Core initialization.
Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.
Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.
Factory Configuration (FCFG)
9-36.
20 19 18 17
4 3 2 1
SLDO_TRIM_OUTPUT
R-3Fh
Device Configuration
16
0
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