Icemelter - Texas Instruments SimpleLink CC2620 Technical Reference Manual

ICEMelter

Bit Field
1 TapAccessible
0 TapPresent
Value Command
000 Normal Operation
Wait in reset
001
(Extend reset)
010 Reserved
011 Reserved
1xx Cancel
5.4 ICEMelter
ICEMelter wakes up the JTAG power domain, that contains ICEPick and cJTAG modules and monitors
the activities on the TCK-pin. When ICEMelter detects traffic on the TCK-pin (8 rising edges and 8 falling
edges on TCK), it sends a power-up request to the AON WUC that powers up the JTAG power domain.
The emulator must allow power-up time of at least 200 µ for JTAG power domain before sending
remaining commands to JTAG interface.
5.5 Serial Wire Viewer (SWV)
The CPU uses the TPIU macro inside the processor to support the serial wire viewer (SWV) interface (a
single line interface).
The following sequence is needed to enable SWV output on the CPU.
1. Enable trace system by setting CPU_SCS:DEMCR.TRCENA (see
(Offset = DFCh) [reset = X]).
2. Unlock ITM configuration by writing to the Lock Access Register CPU_ITM:LAR (see
LAR Register (Offset = FB0h) [reset = X]).
3. Enable ITM by setting CPU_ITM:TCR.ITMENA (see
[reset = X]).
4. Enable the desired stimulus port (0 to 31) in CPU_ITM:TER (see
(Offset = E00h) [reset = X] ).
5. Change formatter configuration if needed CPU_TPIU:FFCR (see
(Offset = 304h) [reset = X]).
6. Change the pin protocol if needed CPU_TPIU:SPPR (see
F0h) [reset = X]).
7. Set the baudrate in CPU_TPIU:ACPR (see
8. The SWV can be mapped to DIO n by writing the corresponding port ID in the IOC:IOCFGn register
(see ) For more details, refer to
Writes to the CPU_ITM:STIMn registers (assuming that they are enabled) trigger a transmit on SWV
output if the FIFO is not full.
408
JTAG Interface
Table 5-21. Secondary Debug TAP Register (SDTR) (continued)
Width Type
1 R
1 R
Table 5-22. Reset Control
Chapter 11, I/O Control).
Copyright © 2015, Texas Instruments Incorporated
Reset Description
When 0, the TAP cannot be accessed due to security.
–
When 1, the TAP can be accessed.
When 0, there is not a TAP assigned to this spot.
When 1, this TAP exists in the device.
–
If a TAP does not exist, the rest of the controls and status
bits in this register are considered to be nonoperational.
Description
Reset operates under the normal control of the application or device
controls.
The module(s) controlled by this secondary TAP remain in the reset state
when the reset has been asserted. This bit alone does not reset the
processor.
Reserved
Reserved
Cancels reset command lockout
Section
Section 2.7.3.35, TCR Register (Offset = E80h)
Section
Section
Section 2.7.5.4, SPPR Register (Offset =
Section 2.7.5.3, ACPR Register (Offset = 10h) [reset = X]).
SWCU117C – February 2015 – Revised September 2015
www.ti.com
2.7.4.59, DEMCR Register
Section 2.7.3.36,
2.7.3.33, TER Register
2.7.5.6, FFCR Register
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