Fault Escalation And Hard Faults - Texas Instruments SimpleLink CC2620 Technical Reference Manual

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4.2.2 Fault Escalation and Hard Faults

All fault exceptions except for hard fault have configurable exception priority (see CPU_SCS:SHPR1 in
Section 2.7.4.32,SHPR1 Register (Offset = D18h) [reset = X]). Software can disable execution of the
handlers for these faults (see CPU_SCS:SHCSR
[reset = X]).
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another fault
handler as described in
In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority
escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when:
• A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault
occurs because a fault handler cannot preempt itself because it must have the same priority as the
current priority level.
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation
happens because the handler for the new fault cannot preempt the fault handler that is currently
executing.
• An exception handler causes a fault for which the priority is the same as or lower than the exception
that is currently executing.
• A fault occurs and the handler for that fault is not enabled.
NOTE: If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault
does not escalate to a hard fault. Thus, if a corrupted stack causes a fault, the fault handler
executes even though the stack push for the handler failed. The fault handler operates but
the stack contents are corrupted.
4.2.3 Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults, the fault address register indicates
the address accessed by the operation that caused the fault, as shown in
Handler
Hard fault
Bus fault
Usage fault
4.2.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the hard fault handlers. In a
CC26xx and CC13xx device, a lockup state resets the system.
SWCU117C – February 2015 – Revised September 2015
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Section 4.1, Exception Model.
Table 4-5. Fault Status and Fault Address Registers
Status Register Name
Hard Fault Status (HFSR)
Bus Fault Status (BFSR)
Usage Fault Status (UFSR)
Copyright © 2015, Texas Instruments Incorporated
inSection 2.7.4.35, SHCSR Register (Offset = D24h)
Table
Address Register Name
–
Bus Fault Address (BFAR)
–
Fault Handling
4-5.
Register Description
See Section 2.7.4.37, HFSR
Register (Offset = D2Ch) [reset
= X]
See Section 2.7.4.40, BFAR
Register (Offset = D38h) [reset
= 0h]
–
237
Interrupts and Events