Texas Instruments SimpleLink CC2620 Technical Reference Manual page 170

Cortex-M3 Processor Registers
2.7.4.30 SCR Register (Offset = D10h) [reset = 0h]
SCR is shown in Figure 2-100
System Control
This register is used for power-management functions, i.e., signaling to the system when the processor
can enter a low power state, controlling how the processor enters and exits low power states.
31 30
23 22
15 14
7 6
RESERVED
R/W-0h
Bit Field
31-5 RESERVED
4 SEVONPEND
3 RESERVED
2 SLEEPDEEP
1 SLEEPONEXIT
0 RESERVED
170
and described in Table
Figure 2-100. SCR Register
29 28
RESERVED
R/W-0h
21 20
RESERVED
R/W-0h
13 12
RESERVED
R/W-0h
5 4
SEVONPEND RESERVED
R/W-0h
Table 2-126. SCR Register Field Descriptions
Type Reset Description
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h Send Event on Pending bit:
0: Only enabled interrupts or events can wakeup the processor,
disabled interrupts are excluded
1: Enabled events and all interrupts, including disabled interrupts,
can wakeup the processor.
When an event or interrupt enters pending state, the event signal
wakes up the processor from WFE. If
the processor is not waiting for an event, the event is registered and
affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h
Controls whether the processor uses sleep or deep sleep as its low
power mode
0h = Sleep
1h = Deep sleep
R/W 0h Sleep on exit when returning from Handler mode to Thread mode.
Enables interrupt driven applications to avoid returning to empty
main application.
0: Do not sleep when returning to thread mode
1: Sleep on ISR exit
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Copyright © 2015, Texas Instruments Incorporated
2-126.
27 26
19 18
11 10
3 2
SLEEPDEEP
R/W-0h R/W-0h
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
9 8
1 0
SLEEPONEXIT RESERVED
R/W-0h R/W-0h
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