Texas Instruments SimpleLink CC2620 Technical Reference Manual page 185

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2.7.4.42 ID_PFR0 Register (Offset = D40h) [reset = 30h]
ID_PFR0 is shown in
Processor Feature 0
31 30 29 28
15 14 13 12
RESERVED
Bit Field
31-8 RESERVED
7-4 STATE1
3-0 STATE0
SWCU117C – February 2015 – Revised September 2015
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Figure 2-112 and described in
Figure 2-112. ID_PFR0 Register
27 26 25
11 10 9
R-0h
Table 2-138. ID_PFR0 Register Field Descriptions
Type Reset
R 0h
R 3h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-138.
24 23 22 21
RESERVED
R-0h
8 7 6 5
STATE1
R-3h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
State1 (T-bit == 1)
0x0: N/A
0x1: N/A
0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit
Buncond/BL but no other 32-bit basic instructions (Note non-basic
32-bit instructions can be added using the appropriate instruction
attribute, but other 32-bit basic instructions cannot.)
0x3: Thumb-2 encoding with all Thumb-2 basic instructions
State0 (T-bit == 0)
0x0: No ARM encoding
0x1: N/A
Cortex-M3 Processor Registers
20 19 18 17
4 3 2 1
STATE0
R-0h
16
0
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