Texas Instruments SimpleLink CC2620 Technical Reference Manual page 531

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6.2.4.56 RAMRETEN Register (Offset = 224h) [reset = 3h]
RAMRETEN is shown in
Memory Retention Control
31 30 29 28
15 14 13 12
Bit Field
31-3 RESERVED
2 RFC
1-0 VIMS
SWCU117C – February 2015 – Revised September 2015
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Figure 6-95 and described in
Figure 6-95. RAMRETEN Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
RESERVED
R-0h
Table 6-100. RAMRETEN Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 3h
Copyright © 2015, Texas Instruments Incorporated
Table 6-100.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
0: Retention for RFC SRAM disabled
1: Retention for RFC SRAM enabled
0: Memory retention disabled
1: Memory retention enabled
Bit 0: VIMS_TRAM
Bit 1: VIMS_CRAM
Legal modes depend on settings in VIMS:CTL.MODE
00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted
- must be set to CACHE or SPLIT mode after waking up again
01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is
asserted. Must remain in GPRAM mode after wake up, alternatively
select OFF mode first and then CACHE or SPILT mode.
10: Illegal mode
11: No restrictions
Power, Reset, and Clock Management
PRCM Registers
19 18 17 16
3 2 1 0
RFC VIMS
R/W- R/W-3h
0h
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