Texas Instruments SimpleLink CC2620 Technical Reference Manual page 77

www.ti.com
2.7.2 CPU_FPB Registers
Table 2-47 lists the memory-mapped registers for the CPU_FPB. All register offset addresses not listed in
Table 2-47 must be considered as reserved locations and the register contents must not be modified.
Offset Acronym
0h CTRL
4h REMAP
8h COMP0
Ch COMP1
10h COMP2
14h COMP3
18h COMP4
1Ch COMP5
20h COMP6
24h COMP7
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Table 2-47. CPU_FPB Registers
Register Name
Control
Remap
Comparator 0
Comparator 1
Comparator 2
Comparator 3
Comparator 4
Comparator 5
Comparator 6
Comparator 7
Copyright © 2015, Texas Instruments Incorporated
Cortex-M3 Processor Registers
Section
Section 2.7.2.1
Section 2.7.2.2
Section 2.7.2.3
Section 2.7.2.4
Section 2.7.2.5
Section 2.7.2.6
Section 2.7.2.7
Section 2.7.2.8
Section 2.7.2.9
Section 2.7.2.10
77