Texas Instruments SimpleLink CC2620 Technical Reference Manual page 160

Cortex-M3 Processor Registers
2.7.4.21 NVIC_IPR4 Register (Offset = 410h) [reset = 0h]
NVIC_IPR4 is shown in
Irq 16 to 19 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_19
R/W-0h
Bit Field
31-24 PRI_19
23-16 PRI_18
15-8 PRI_17
7-0 PRI_16
160
Figure 2-91 and described in
Figure 2-91. NVIC_IPR4 Register
PRI_18
R/W-0h
Table 2-117. NVIC_IPR4 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-117.
9
PRI_17
R/W-0h
Description
Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details).
Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details).
Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details).
Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details).
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8 7 6 5 4 3 2 1
PRI_16
R/W-0h
Submit Documentation Feedback
0