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4.7.2.19 CPUIRQSEL18 Register (Offset = 48h) [reset = 13h]
CPUIRQSEL18 is shown in
Output Selection for CPU Interrupt 18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
Field
31-7
RESERVED
6-0
EV
SWCU117C – February 2015 – Revised September 2015
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Figure 4-28
and described in
Figure 4-28. CPUIRQSEL18 Register
RESERVED
R-0h
Table 4-33. CPUIRQSEL18 Register Field Descriptions
Type
Reset
R
0h
R
13h
Copyright © 2015, Texas Instruments Incorporated
Table
4-33.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Read only selection value
13h = GPT1B interrupt event, controlled by GPT1:TBMR
Interrupts and Events Registers
8
7
6
5
4
3
2
1
EV
R-13h
Interrupts and Events
0
291