Exceptions And Interrupts - Texas Instruments SimpleLink CC2620 Technical Reference Manual

Programming Model
2.4.1 Processor Mode and Privilege Levels for Software Execution
The Cortex-M3 processor has two modes of operation:
• Thread mode executes application software. The processor enters thread mode when it comes out of
reset.
• Handler mode handles exceptions. When the processor completes exception processing, it returns to
thread mode.
In addition, the Cortex-M3 processor has two privilege levels, unprivileged and privileged.
• In unprivileged mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or SCB
• In privileged mode, software can use all the instructions and has access to all resources in the
processor.
In thread mode, the CONTROL register (see
or unprivileged. In handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to
transfer control to privileged software.
2.4.2 Stacks
The Cortex-M3 processor uses a full descending stack, meaning that the stack pointer indicates the last
stacked item on the memory. When the processor pushes a new item onto the stack, it decrements the
stack pointer and then writes the item to the new memory location. The processor implements two stacks,
the main stack and the process stack, with a pointer for each held in independent registers (see the SP
register in Table 2-16).
In thread mode, the CONTROL register (see
stack or the process stack. In handler mode, the processor always uses the main stack.
options for processor operations.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode
Thread
Handler
(1)
See the CONTROL register

2.4.3 Exceptions and Interrupts

An exception changes the normal flow of software control. The support for interrupts and system
exceptions is implemented by using the built-in NVIC, which supports up to 240 external interrupt inputs.
Besides the external interrupts, the Cortex-M3 also services 16 predefined exception sources including
Reset, NMI, and so on. The processor and the NVIC prioritize and handle all exceptions. The processor
uses handler mode to handle all exceptions, except for reset. Software configures the actual priorities
assigned to NVIC external interrupt inputs through registers.
2.4.4 Data Types
The Cortex-M3 processor supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also
supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. For
more information, see the Cortex-M3/M4F Instruction Set Technical User's Manual (SPMU159).
32
The Cortex-M3 Processor
Table
Table
Use
Applications
Exception handlers
(Table 2-24).
Copyright © 2015, Texas Instruments Incorporated
2-24) controls whether software execution is privileged
2-24) controls whether the processor uses the main
Privilege Level
(1)
Privileged or unprivileged
Always privileged
SWCU117C – February 2015 – Revised September 2015
www.ti.com
Table 2-1 lists the
Stack Used
Main stack or process stack
Main stack
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