Texas Instruments SimpleLink CC2620 Technical Reference Manual page 785

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9.2.1.64 AMPCOMP_CTRL1 Register (Offset = 378h) [reset = FF183F47h]
AMPCOMP_CTRL1 is shown in
Amplitude Compensation Control
31 30
RESERVED AMPCOMP_RE
Q_MODE
R-1h R-1h
23 22
IBIAS_OFFSET
15 14
7 6
CAP_STEP
Bit Field
31 RESERVED
30 AMPCOMP_REQ_MODE
29-24 RESERVED
23-20 IBIAS_OFFSET
19-16 IBIAS_INIT
15-8 LPM_IBIAS_WAIT_CNT_
FINAL
7-4 CAP_STEP
3-0 IBIASCAP_HPTOLP_OL_ R
CNT
SWCU117C – February 2015 – Revised September 2015
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Figure 9-86
Figure 9-86. AMPCOMP_CTRL1 Register
29 28
21 20
R-1h
13 12
LPM_IBIAS_WAIT_CNT_FINAL
5 4
R-4h
Table 9-88. AMPCOMP_CTRL1 Register Field Descriptions
Type Reset
R 1h
R 1h
R 3Fh
R 1h
R 8h
R 3Fh
R 4h
7h
Copyright © 2015, Texas Instruments Incorporated
and described in Table 9-88.
27
RESERVED
R-3Fh
19
11
R-3Fh
3
IBIASCAP_HPTOLP_OL_CNT
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Trim value for
DDI_0_OSC:AMPCOMPCTL.AMPCOMP_REQ_MODE.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Offset values of XOSC IBIAS trim. IBIAS trim value would always be
greater than or equal to this offset in both HPM and LPM.
Initial value of XOSC IBIAS trim. During ramping up, IBIAS is set to
IBIAS_OFFSET + IBIAS_INIT.
FSM waits for ddi_lpm_ibias_wait_cnt_final clock cycles in
IDAC_DECREMENT_WITH_MEASURE states in order to
compensate slow response of the xtal. 8-bits.
Step size of XOSC CAP trim (both Q1 and Q2) during XOSC mode
transition. Can vary from 6 to 12. Other values are possible but not
valid.
During HPM to LPM transition, CAP trim and IBIAS trim must be
modified by this amount. IBIAS and CAP trim open loop count.
CAP_REM is remainder of the CAP that is left to reach the final cap
value. Do not need to program this.
CAP_TRIM = CAP_INIT -
CAP_STEP*IBIASCAP_HPTOLP_OL_CNT - CAP_REM
IBIAS_TRIM = IBIAS_INIT - 1*IBIASCAP_HPTOLP_OL_CNT
Here, cap_init is decimal conversion of cap_init_col and
cap_init_row.
Factory Configuration (FCFG)
26 25
18 17
IBIAS_INIT
R-8h
10 9
2 1
R-7h
Device Configuration
24
16
8
0
785