Texas Instruments SimpleLink CC2620 Technical Reference Manual page 41

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Address Offset
Physical Address
Description
Also referred to as xPSR
The Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions:
• Application Program Status Register (APSR), bits 31–27
• Execution Program Status Register (EPSR), bits 26–24, 15–10
• Interrupt Program Status Register (IPSR), bits 6–0
The PSR, IPSR, and EPSR registers can be accessed only in privileged mode; the APSR register can be accessed in privileged or
unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the if-then (IT) instruction or the interruptible-continuable instruction (ICI)
field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the
MSR instruction always return 0. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault
handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see
Return).
IPSR contains the exception type number of the current ISR.
These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument
to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be
written to using APSR with the MSR instruction.
instruction descriptions in the Cortex-M3/M4F Instruction Set Technical User's Manual (SPMU159) for more information about how to
access the program status registers.
Type
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
N Z C V Q ICI / IT
Bits Field Name
31 N
30 Z
29 C
SWCU117C – February 2015 – Revised September 2015
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Table 2-20. Program Status Register (PSR) or (xPSR)
Table 2-20 shows the possible register combinations for the PSR. See the MRS and MSR
R/W
RESERVED
Description
APSR Negative or Less Flag
Value Description
1 The previous operation result was negative or less
than.
0 The previous operation result was positive, zero,
greater than, or equal
The value of this bit is meaningful only when accessing PSR or
APSR.
APSR Zero Flag
Value Description
1 The previous operation result was zero.
0 The previous operation result was nonzero.
The value of this bit is meaningful only when accessing PSR or
APSR.
APSR Carry or Borrow Flag
Value Description
1 The previous add operation resulted in a carry bit or
the previous subtract operation did not result in a
borrow bit.
0 The previous add operation did not result in a carry
bit or the previous subtract operation resulted in a
borrow bit.
The value of this bit is meaningful only when accessing PSR or
APSR.
Copyright © 2015, Texas Instruments Incorporated
Reset
Instance
9
ICI / IT
Cortex-M3 Core Registers
0x0100 0000
Section 4.1.7, Exception Entry and
8 7 6 5 4 3 2 1
ISRNUM
Type Reset
R/W 0
R/W 0
R/W 0
0
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