Texas Instruments SimpleLink CC2620 Technical Reference Manual page 199

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2.7.4.56 DHCSR Register (Offset = DF0h) [reset = X]
DHCSR is shown in
Debug Halting Control and Status
The purpose of this register is to provide status information about the state of the processor, enable core
debug, halt and step the processor. For writes, 0xA05F must be written to higher half-word of this register,
otherwise the write operation is ignored and no bits are written into the register. If not enabled for Halting
mode, C_DEBUGEN = 1, all other fields are disabled. This register is not reset on a core reset. It is reset
by a power-on reset. However, C_HALT always clears on a core reset. To halt on a reset, the following
bits must be enabled: DEMCR.VC_CORERESET and C_DEBUGEN. Note that writes to this register in
any size other than word are unpredictable. It is acceptable to read in any size, and it can be used to
avoid or intentionally change a sticky bit.
Behavior of the system when writing to this register while CPU is halted (i.e. C_DEBUGEN = 1 and
S_HALT= 1):
C_HALT=0, C_STEP=0, C_MASKINTS=0 Exit Debug state and start instruction execution. Exceptions
activate according to the exception configuration rules.
C_HALT=0, C_STEP=0, C_MASKINTS=1 Exit Debug state and start instruction execution. PendSV,
SysTick and external configurable interrupts are disabled, otherwise exceptions activate according to
standard configuration rules.
C_HALT=0, C_STEP=1, C_MASKINTS=0 Exit Debug state, step an instruction and halt. Exceptions
activate according to the exception configuration rules.
C_HALT=0, C_STEP=1, C_MASKINTS=1 Exit Debug state, step an instruction and halt. PendSV, SysTick
and external configurable interrupts are disabled, otherwise exceptions activate according to standard
configuration rules.
C_HALT=1, C_STEP=x, C_MASKINTS=x Remain in Debug state
31 30
23 22
RESERVED
15 14
7 6
RESERVED
R-0h
Bit Field
31-26 RESERVED
25 S_RESET_ST
SWCU117C – February 2015 – Revised September 2015
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Figure 2-126 and described in
Figure 2-126. DHCSR Register
29 28
RESERVED
R/W-0h
21 20
R/W-0h
13 12
5 4
C_SNAPSTALL RESERVED
R/W-0h R/W-0h
Table 2-152. DHCSR Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-152.
27
19
S_LOCKUP S_SLEEP
R/W-0h R/W-0h
11
RESERVED
R-0h
3
C_MASKINTS C_STEP
R/W-0h R/W-0h
Description
Software must not rely on the value of a reserved.
When writing to this register, 0x28 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.
Indicates that the core has been reset, or is now being reset, since
the last time this bit was read. This a sticky bit that clears on read.
So, reading twice and getting 1 then 0 means it was reset in the
past. Reading twice and getting 1 both times means that it is being
reset now (held in reset still).
When writing to this register, 0 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.
Cortex-M3 Processor Registers
26 25
S_RESET_ST S_RETIRE_ST
R/W-0h
18 17
S_HALT S_REGRDY
R/W-0h
10 9
2 1
C_HALT C_DEBUGEN
R/W-0h
24
R/W-0h
16
R/W-X
8
0
R/W-0h
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