Texas Instruments SimpleLink CC2620 Technical Reference Manual page 204

Cortex-M3 Processor Registers
2.7.4.59 DEMCR Register (Offset = DFCh) [reset = 0h]
DEMCR is shown in
Debug Exception and Monitor Control
The purpose of this register is vector catching and debug monitor control. This register manages
exception behavior under debug. Vector catching is only available to halting debug. The upper halfword is
for monitor controls and the lower halfword is for halting exception support. This register is not reset on a
system reset. This register is reset by a power-on reset. The fields MON_EN, MON_PEND, MON_STEP
and MON_REQ are always cleared on a core reset. The debug monitor is enabled by software in the reset
handler or later, or by the **AHB-AP** port. Vector catching is semi-synchronous. When a matching event
is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait
until the next instruction boundary. As a result, it stops on the first instruction of the exception handler.
However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during a vector
read or stack push error the halt occurs on the corresponding fault handler for the vector error or stack
push. 2. If a late arriving interrupt detected during a vector read or stack push error it is not taken. That is,
an implementation that supports the late arrival optimization must suppress it in this case.
31 30
23 22
RESERVED
15 14
7 6
VC_STATERR VC_CHKERR
R/W-0h R/W-0h
Bit Field
31-25 RESERVED
24 TRCENA
23-20 RESERVED
19 MON_REQ
18 MON_STEP
17 MON_PEND
204
Figure 2-129 and described in
Figure 2-129. DEMCR Register
29 28
RESERVED
R/W-0h
21 20
R/W-0h
13 12
RESERVED
R/W-0h
5 4
VC_NOCPERR VC_MMERR
R/W-0h R/W-0h
Table 2-155. DEMCR Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-155.
27 26
19 18
MON_REQ MON_STEP
R/W-0h R/W-0h
11 10
VC_HARDERR
R/W-0h
3 2
RESERVED
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
This bit must be set to 1 to enable use of the trace and debug
blocks: DWT, ITM, ETM and TPIU. This enables control of power
usage unless tracing is required. The application can enable this, for
ITM use, or use by a debugger.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
This enables the monitor to identify how it wakes up. This bit clears
on a Core Reset.
0x0: Woken up by debug exception.
0x1: Woken up by MON_PEND
When MON_EN = 1, this steps the core. When MON_EN = 0, this bit
is ignored.
This is the equivalent to DHCSR.C_STEP. Interrupts are only
stepped according to the priority of the monitor and settings of
PRIMASK, FAULTMASK, or BASEPRI.
Pend the monitor to activate when priority permits. This can wake up
the monitor through the AHB-AP port. It is the equivalent to
DHCSR.C_HALT for Monitor debug. This register does not reset on
a system reset. It is only reset by a power-on reset. Software in the
reset handler or later, or by the DAP must enable the debug monitor.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
TRCENA
R/W-0h
17 16
MON_PEND MON_EN
R/W-0h R/W-0h
9 8
VC_INTERR VC_BUSERR
R/W-0h R/W-0h
1 0
VC_CORERES
ET
R/W-0h
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