Texas Instruments SimpleLink CC2620 Technical Reference Manual page 804

AES Cryptoprocessor Overview
Physical Address Register Name
0x4002 401C DMASWRESET
0x4002 4020 DMACH1CTL
0x4002 4024 DMACH1EXTADDR
0x4002 402C DMACH1LEN
0x4002 4078 DMABUSCFG
0x4002 407C DMAPORTERR
0x4002 40F8 DMAHWOPT
0x4002 40FC DMAHWVER
Key-Storage Registers
0x4002 4400 KEYWRITEAREA
0x4002 4404 KEYWRITTENAREA
0x4002 4408 KEYSIZE
0x4002 440C KEYREADAREA
AES Engine Registers
0x4002 4500 to AESKEY2_0 to AESKEY2_3
0x4002 450C
0x4002 4510 to AESKEY3_0 to AESKEY3_3
0x4002 451C
0x4002 4540 to AESIV_0 to AESIV_3
0x4002 454C
0x4002 4550 AESCTL
0x4002 4554 AESDATALEN0
0x4002 4558 AESDATALEN1
0x4002 455C AESAUTHLEN
0x4002 4560 AESDATAIN0
0x4002 4560 AESDATAOUT0
0x4002 4564 AESDATAIN1
0x4002 4564 AESDATAOUT1
0x4002 4568 AESDATAIN2
0x4002 4568 AESDATAOUT2
0x4002 456C AESDATAIN3
0x4002 456C AESDATAOUT3
0x4002 4570 to AESTAGOUT_0 to
0x4002 4057C AESTAGOUT_3
Master-Control Registers
0x4002 4700 ALGSEL
0x4002 4704 DMAPROTCTL
0x4002 4740 SWRESET
804 Cryptography
Table 10-1. Detailed Memory Map (continued)
Type
W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
W
W
R/W
R/W
W
W
W
W
R
W
R
W
R
W
R
W
R/W
R/W
W
Copyright © 2015, Texas Instruments Incorporated
Reset Value Remark
0x0000 0000 DMAC software
reset
0x0000 0000 Channel 1 control
register
0x0000 0000 Channel 1 external
address
0x0000 0000 Channel 1 DMA
length
0x0000 6000 Master run-time
parameters
0x0000 0000 Port-error raw-status
register
0x0000 0202 DMAC-options
register
0x0101 2ED1 DMAC-version
register
0x0000 0000 Writer-area register
0x0000 0000 Written-area register
0x0000 0001 Key-size register
0x0000 0008 Read-area register
0x0000 0000 Clear/wipe
AESKEY2__0 to
AESKEY2__3
register
0x0000 0000 Clear/wipe
AESKEY3__0 to
AESKEY3__3
register
0x0000 0000 AES IV (LSW)
0x8000 0000 I/O and control mode
0x0000 0000 Crypto data length
(LSW)
0x0000 0000 Crypto data length
(MSW)
0x0000 0000 AAD data length
0x0000 0000 Data input (LSW)
0x0000 0000 Data output (LSW)
0x0000 0000 Data input
0x0000 0000 Data output
0x0000 0000 Data input
0x0000 0000 Data output
0x0000 0000 Data input (MSW)
0x0000 0000 Data output (MSW)
0x0000 0000 Tag output (LSW)
0x0000 0000 Algorithm selection
0x0000 0000 Enable privileged
access on master
0x0000 0000 Master-control
software reset
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
www.ti.com
Link
Section 10.2.1.5
Section 10.2.1.6
Section 10.2.1.7
Section 10.2.1.8
Section 10.2.1.9
Section 10.2.1.10
Section 10.2.1.11
Section 10.2.1.12
Section 10.2.1.13
Section 10.2.1.14
Section 10.2.1.15
Section 10.2.1.16
Section 10.2.1.17
Section 10.2.1.18
Section 10.2.1.19
Section 10.2.1.20
Section 10.2.1.21
Section 10.2.1.22
Section 10.2.1.24
Section 10.2.1.23
Section 10.2.1.26
Section 10.2.1.25
Section 10.2.1.28
Section 10.2.1.27
Section 10.2.1.30
Section 10.2.1.29
Section 10.2.1.31
Section 10.2.1.32
Section 10.2.1.33
Section 10.2.1.34