Texas Instruments SimpleLink CC2620 Technical Reference Manual page 129

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Offset Acronym
D4Ch ID_AFR0
D50h ID_MMFR0
D54h ID_MMFR1
D58h ID_MMFR2
D5Ch ID_MMFR3
D60h ID_ISAR0
D64h ID_ISAR1
D68h ID_ISAR2
D6Ch ID_ISAR3
D70h ID_ISAR4
D88h CPACR
DF0h DHCSR
DF4h DCRSR
DF8h DCRDR
DFCh DEMCR
F00h STIR
SWCU117C – February 2015 – Revised September 2015
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Table 2-96. CPU_SCS Registers (continued)
Register Name
Auxiliary Feature 0
Memory Model Feature 0
Memory Model Feature 1
Memory Model Feature 2
Memory Model Feature 3
ISA Feature 0
ISA Feature 1
ISA Feature 2
ISA Feature 3
ISA Feature 4
Coprocessor Access Control
Debug Halting Control and Status
Deubg Core Register Selector
Debug Core Register Data
Debug Exception and Monitor Control
Software Trigger Interrupt
Copyright © 2015, Texas Instruments Incorporated
Cortex-M3 Processor Registers
Section
Section 2.7.4.45
Section 2.7.4.46
Section 2.7.4.47
Section 2.7.4.48
Section 2.7.4.49
Section 2.7.4.50
Section 2.7.4.51
Section 2.7.4.52
Section 2.7.4.53
Section 2.7.4.54
Section 2.7.4.55
Section 2.7.4.56
Section 2.7.4.57
Section 2.7.4.58
Section 2.7.4.59
Section 2.7.4.60
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