Texas Instruments SimpleLink CC2620 Technical Reference Manual page 200

Cortex-M3 Processor Registers
Table 2-152. DHCSR Register Field Descriptions (continued)
Bit Field
24 S_RETIRE_ST
23-20 RESERVED
19 S_LOCKUP
18 S_SLEEP
17 S_HALT
16 S_REGRDY
15-6 RESERVED
5 C_SNAPSTALL
4 RESERVED
3 C_MASKINTS
2 C_STEP
1 C_HALT
200
Type Reset Description
R/W 0h Indicates that an instruction has completed since last read. This is a
sticky bit that clears on read. This determines if the core is stalled on
a load/store or fetch.
When writing to this register, 0 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.
R/W 0h Software must not rely on the value of a reserved.
When writing to this register, 0x5 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.
R/W 0h Reads as one if the core is running (not halted) and a lockup
condition is present.
When writing to this register, 1 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.
R/W 0h Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-
EXIT**). Must use C_HALT to gain control or wait for interrupt to
wake-up.
When writing to this register, 1 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.
R/W 0h The core is in debug state when this bit is set.
When writing to this register, 1 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.
R/W X Register Read/Write on the Debug Core Register Selector register is
available. Last transfer is complete.
When writing to this register, 1 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.
R 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h
If the core is stalled on a load/store operation the stall ceases and
the instruction is forced to complete. This enables Halting debug to
gain control of the core. It can only be set if: C_DEBUGEN = 1 and
C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates
that no instruction has advanced. This prevents misuse. The bus
state is Unpredictable when this is used. S_RETIRE_ST can detect
core stalls on load/store operations.
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h
Mask interrupts when stepping or running in halted debug. This
masking does not affect NMI, fault exceptions and SVC caused by
execution of the instructions. This bit must only be modified when
the processor is halted (S_HALT == 1). C_MASKINTS must be set
or cleared before halt is released (i.e., the writes to set or clear
C_MASKINTS and to set or clear C_HALT must be separate).
Modifying C_MASKINTS while the system is running with halting
debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause
unpredictable behavior.
R/W 0h Steps the core in halted debug. When C_DEBUGEN = 0, this bit has
no effect. Must only be modified when the processor is halted
(S_HALT == 1).
Modifying C_STEP while the system is running with halting debug
support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause
unpredictable behavior.
R/W 0h
Halts the core. This bit is set automatically when the core Halts. For
example Breakpoint. This bit clears on core reset.
Copyright © 2015, Texas Instruments Incorporated
SWCU117C – February 2015 – Revised September 2015
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