Texas Instruments SimpleLink CC2620 Technical Reference Manual page 191

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2.7.4.48 ID_MMFR2 Register (Offset = D58h) [reset = 1000000h]
ID_MMFR2 is shown in
Memory Model Feature 2
General information on the memory model and memory management support.
31 30
23 22
15 14
7 6
Bit Field
31-25 RESERVED
24 WAIT_FOR_INTERRUPT
_STALLING
23-0 RESERVED
SWCU117C – February 2015 – Revised September 2015
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Figure 2-118 and described in
Figure 2-118. ID_MMFR2 Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 2-144. ID_MMFR2 Register Field Descriptions
Type Reset
R 0h
R 1h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-144.
27 26
19 18
11 10
3 2
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
wait for interrupt stalling
0x0: Not supported
0x1: Wait for interrupt supported
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Cortex-M3 Processor Registers
25 24
WAIT_FOR_IN
TERRUPT_ST
ALLING
R-1h
17 16
9 8
1 0
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